MaPU: A Novel Mathematical Computing Architecture | |
Donglin Wang; Shaolin Xie; Zhiwei Zhang; Xueliang Du; Lei Wang; Zijun Liu; shaolin.xie@ia.ac.cn | |
2016-03 | |
会议名称 | the 22nd IEEE Symposium on High Performance Computer Architecture |
会议录名称 | http://hpca22.site.ac.upc.edu |
会议日期 | March 12-16 2016 |
会议地点 | Barcelona, Spain |
出版者 | IEEE |
摘要 | As the feature size of the semiconductor process is scaling down to 10nm and below, it is possible to assemble systems with high performance processors that can theoretically provide computational power of up to tens of PLOPS. However, the power consumption of these systems is also rocketing up to tens of millions watts, and the actual performance is only around 60% of the theoretical performance. Today, power efficiency and sustained performance have become the main concern of processor designers. Traditional computing architecture such as superscalar and GPGPU are proven to be power inefficient, and there is a big gap between the actual and peak performance. In this paper, we present the MaPU architecture, a novel architecture which is suitable for data-intensive computing with great power efficiency and sustained computation throughput. To achieve this goal, MaPU attempts to optimize the application from a system perspective, including the hardware, algorithm and corresponding program model. It uses an innovative multi-granularity parallel memory system with intrinsic shuffle ability, cascading pipelines with wide SIMD data paths and a state-machine-based program model. When executing typical signal processing algorithms, a single MaPU core implemented with a 40nm process exhibits a sustained performance of 134 GLOPS while consuming only 2.8 W in power, which increases the actual power efficiency by an order of magnitude comparable with the traditional CPU and GPGPU. |
关键词 | Computer Architecture Vlsi High Performance Computing |
学科领域 | Computer Science |
收录类别 | SCI |
语种 | 英语 |
文献类型 | 会议论文 |
条目标识符 | http://ir.ia.ac.cn/handle/173211/10916 |
专题 | 国家专用集成电路设计工程技术研究中心 |
通讯作者 | shaolin.xie@ia.ac.cn |
作者单位 | Institute of Automation, Chinese Academy of Sciences |
第一作者单位 | 中国科学院自动化研究所 |
推荐引用方式 GB/T 7714 | Donglin Wang,Shaolin Xie,Zhiwei Zhang,et al. MaPU: A Novel Mathematical Computing Architecture[C]:IEEE,2016. |
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文件名称/大小 | 文献类型 | 版本类型 | 开放类型 | 使用许可 | ||
main-camera-ready.pd(2051KB) | 会议论文 | 开放获取 | CC BY-NC-SA | 浏览 |
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