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可定制嵌入式计算机加固技术研究
郑美松
学位类型工学博士
导师李立健
2016-05-27
学位授予单位中国科学院大学
学位授予地点北京
关键词嵌入式系统 容错 可定制 单粒子翻转
摘要可定制嵌入式计算机具有可裁剪、体系结构灵活、便于加固等优点,其价值逐渐受到工业、军事、航天等领域的重视。本文在深入分析国内外研究现状的基础上,围绕着可定制嵌入式计算机设计的关键技术问题开展研究,主要工作体现在以下几个方面:
1. 可定制嵌入式计算机体系结构分析
研究嵌入式计算机体系结构设计方法,从处理器、存储和总线三方面分析影响计算机性能的因素。采用MiBench嵌入式基准程序对微处理器功能部件、Cache性能和总线性能进行量化分析,为可定制嵌入式计算机设计提供依据。可定制嵌入式计算机主要基于可编程器件实现,为此分析了软核处理器的性能与特点,讨论了可重用IP核的设计方法与实现手段,研究了可编程芯片结构特性以及相应的容错技术。
2. 可编程芯片加固技术研究
针对可定制嵌入式计算机空间应用中的SEU缓解问题,选取一种结构层次清晰的FPGA简化模型,基于该模型,结合无关配置位的统计方法,提出了一种FPGA选择性三模冗余加固方法DC_STMR。实验结果表明,与全三模冗余相比DC_STMR可节省30%的硬件开销,并保证了一定的可靠性,取得了可靠性与开销之间的平衡。
根据电路故障的可控性,提出了一种利用与或逻辑做表决器的FPGA选择性双模冗余故障屏蔽方法DAO。提出了一种FPGA应用电路的故障可控性、可观测性计算方法,以此为依据可计算电路中查找表的故障敏感性,根据故障敏感性判断查找表是否需要冗余以及冗余后的表决方式。DAO方法可根据参数设计1~2倍于原始电路硬件开销的加固电路。
将DAO方法与选择性三模冗余相结合,得到一种FPGA组合加固方法DAT。DAT方法可根据参数设计2~3倍于原始电路开销的加固电路,也可根据对电路可靠性的具体要求制定开销比例。实验结果表明,DAT方法能在DAO的基础上进一步提高电路可靠性。
提出了一种利用FPGA中闲置的进位链逻辑与多路器资源设计双模冗余与三模冗余表决器的方法,使得表决器的插入不会对电路引入额外的硬件开销,从而可以实现低开销的细粒度FPGA冗余设计。根据对可编程器件结构的分析,利用FPGA原语设计了基于故障注入的加固效果验证方法,证明了本文所提出加固方法的实际可行性与有效性。
3. 基于可定制技术的星载图像处理机设计
在深入研究可定制嵌入式计算机体系结构和加固技术的基础上,根据对地观测卫星的特点,结合空间图像处理需求,设计了一种基于FPGA和DSP的可定制嵌入式计算机系统。该系统具有结构灵活性强、空间环境下可靠的优点。
其他摘要

With the merit of scalability, flexible architecture and easy-to-hardening, customizable embedded computer is getting more and more attention in industry, military, aerospace and so on. Based on in-depth analysis on the present research, this dissertation studied the key techniques of customizable embedded computer design, the major contributions of this paper include:
1. Architectural analysis of customizable embedded computer
This dissertation investigated techniques of embedded computer architecture design, and analysed affecting factors of computer performance from aspects of processor, memory and bus. MiBench benchmarks are used to quantitatively evaluate functional units, cache and bus performance of a microcomputer, which is the base of customizable embedded computer designing. Since customizable embedded computers are commonly based on programmable devices, this paper further analyzed the performance and features of soft-core processors, discussed the designing method and implementing approach of reusable IP cores, studied the structural features and relating fault tolerance techniques of programmable chips.
2. Research on FPGA hardening techniques
Choosing an FPGA model with clear hierarchy aims at SEU mitigation for customizable embedded computer in aerospace applications, based on this model, combined with don’t care configuration bits statistics, a selective TMR hardening method (DC_STMR) is proposed. Experimental results show that DC_STMR can reduce failure rates by 3.5x on average compared with the original circuit, and reduce 30% hardware overhead compared with full TMR method.
Based on the controllability of fault propagation, a selective dual module redundancy method with AND/OR logic voter for FPGA hardening (DAO) is proposed. To begin with, a fault propagation controllability and observability computing method for FPGA application circuits is provided, then, LUT fault sensitivities are computed based on the controllability and observability, providing basis for whether or not an LUT has to be duplicate and the voter designing method if duplicated. DAO provides hardening circuits with an overhead of 1~2x according to the parameter setting. As the experimental results suggest, DAO can reduce failure rates by 9.5x on average with an overhead of 2x.
A hybrid FPGA hardening scheme DAT is proposed by combining DAO and selective TMR methods. According to the parameter setting, the overhead of DAT hardening circuits can be set at 2~3 times the original, or the overhead can be designed by reliability requirements. The experimental results showed that DAT method further improves the circuit reliability on the basis of DAO.
A voter designing method making use of idle carry chains and multiplexers in FPGA is provided, the insertion of voters brings about no extra overhead; hence realize fine gain FPGA redundancy design. According to the analysis of configurable device structure, a verfication method based on fault injection is designed with FPGA primitive, certifying the practical feasibility and effectiveness of proposed methods in this dissertation.
3. Space-borne image processor design based on customizable technique
With the overall consideration of earth observation satellite characteristic and space image processing requirement, on the basis of deeply study of customizable embedded architecture and related hardening technique, a customizable embedded system using FPGA and DSP is designed. The provided system has a high flexibility in structure and reliability in space environment.
 

语种中文
文献类型学位论文
条目标识符http://ir.ia.ac.cn/handle/173211/11712
专题毕业生_博士学位论文
作者单位中国科学院自动化研究所
推荐引用方式
GB/T 7714
郑美松. 可定制嵌入式计算机加固技术研究[D]. 北京. 中国科学院大学,2016.
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