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With the merit of scalability, flexible architecture and easy-to-hardening, customizable embedded computer is getting more and more attention in industry, military, aerospace and so on. Based on in-depth analysis on the present research, this dissertation studied the key techniques of customizable embedded computer design, the major contributions of this paper include:
1. Architectural analysis of customizable embedded computer
This dissertation investigated techniques of embedded computer architecture design, and analysed affecting factors of computer performance from aspects of processor, memory and bus. MiBench benchmarks are used to quantitatively evaluate functional units, cache and bus performance of a microcomputer, which is the base of customizable embedded computer designing. Since customizable embedded computers are commonly based on programmable devices, this paper further analyzed the performance and features of soft-core processors, discussed the designing method and implementing approach of reusable IP cores, studied the structural features and relating fault tolerance techniques of programmable chips.
2. Research on FPGA hardening techniques
Choosing an FPGA model with clear hierarchy aims at SEU mitigation for customizable embedded computer in aerospace applications, based on this model, combined with don’t care configuration bits statistics, a selective TMR hardening method (DC_STMR) is proposed. Experimental results show that DC_STMR can reduce failure rates by 3.5x on average compared with the original circuit, and reduce 30% hardware overhead compared with full TMR method.
Based on the controllability of fault propagation, a selective dual module redundancy method with AND/OR logic voter for FPGA hardening (DAO) is proposed. To begin with, a fault propagation controllability and observability computing method for FPGA application circuits is provided, then, LUT fault sensitivities are computed based on the controllability and observability, providing basis for whether or not an LUT has to be duplicate and the voter designing method if duplicated. DAO provides hardening circuits with an overhead of 1~2x according to the parameter setting. As the experimental results suggest, DAO can reduce failure rates by 9.5x on average with an overhead of 2x.
A hybrid FPGA hardening scheme DAT is proposed by combining DAO and selective TMR methods. According to the parameter setting, the overhead of DAT hardening circuits can be set at 2~3 times the original, or the overhead can be designed by reliability requirements. The experimental results showed that DAT method further improves the circuit reliability on the basis of DAO.
A voter designing method making use of idle carry chains and multiplexers in FPGA is provided, the insertion of voters brings about no extra overhead; hence realize fine gain FPGA redundancy design. According to the analysis of configurable device structure, a verfication method based on fault injection is designed with FPGA primitive, certifying the practical feasibility and effectiveness of proposed methods in this dissertation.
3. Space-borne image processor design based on customizable technique
With the overall consideration of earth observation satellite characteristic and space image processing requirement, on the basis of deeply study of customizable embedded architecture and related hardening technique, a customizable embedded system using FPGA and DSP is designed. The provided system has a high flexibility in structure and reliability in space environment.