Parallel Implementation of Arbitrary-Sized Discrete Fourier Transform on FPGA
Shu Lin; Hao,Jie; Li,Chengcheng; Feng,Hui; Wang,Donglin; Shu,Lin
2016-01
会议名称2016 3rd International Conference on Advanced Computing and Communication Systems (ICACCS -2016)
会议录名称2016 3rd International Conference on Advanced Computing and Communication Systems (ICACCS -2016)
会议日期2016.01.22-2016.01.23
会议地点Coimbatore, INDIA
摘要Discrete Fourier Transform(DFT) is one of the frequently used kernels in a variety of signal processing applications. Most previous state-of-the-art work has focused on
the transform size of a power of 2. And many implementations of non-power-of-two sized DFT is customized for a specific application. In this paper, a parallel-processing architecture based on Field-Programmable Gate Array (FPGA) for arbitrary-sized DFT is proposed. In particular, it is attractive to use to compute DFT with arbitrary prime size. A memory efficient data mapping scheme for twiddle factors is proposed, which reduces the storage size of twiddle factors from n2 to kn(k is a constant). We implement a design with 196 processing elements, which is available for any transform size n from 14 to
1024. For a transform size of 59, the throughput in this design can reach to 737.5 Msps. The design can be easily extended to be one with more processing elements if the hardware has enough resources. And we have built a code generator to automatically generate designs with different numbers of processing elements.
关键词Dft Arbitrary-sized Parallel Fpga
收录类别EI
文献类型会议论文
条目标识符http://ir.ia.ac.cn/handle/173211/11726
专题国家专用集成电路设计工程技术研究中心
通讯作者Shu,Lin
作者单位Institute of Automation, Chinese Academy of Sciences
推荐引用方式
GB/T 7714
Shu Lin,Hao,Jie,Li,Chengcheng,et al. Parallel Implementation of Arbitrary-Sized Discrete Fourier Transform on FPGA[C],2016.
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