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DAO: Dual module redundancy with AND/OR logic voter
Zheng, Meisong; Wang, Zilong; Li, Lijian
Conference Name2015 ICRSE & PHM
Source PublicationThe First International Conference on Reliability Systems Engineering
Conference Date2015-10-21
Conference PlaceBeijing
AbstractAs device size shrinks, SRAM-based FPGAs are increasingly prone to be affected by single-event upsets (SEUs). SEU mitigation techniques for FPGAs are mostly expensive in terms of area and power costs. This paper proposes a new design for FPGA hardening using dual-modular redundancy (DMR). The duplication operates on lookup-table (LUT) level, and each pair of identical LUTs will be voted by an AND or OR logic voter. By virtue of the fault-masking effect of AND/OR logic, certain faults in duplicated LUTs will not propagate to the next level of the hardened circuit. Results on MCNC’91 benchmarks show that the proposed method can reduce 90% faults with an area overhead of 100% additional number of LUTs, and the runtime of the proposed algorithm is much shorter than other existing methods. 
KeywordFpga Fault Tolerance Dual Modular Redundancy Fault Sensitivity
Indexed ByEI
Document Type会议论文
Corresponding AuthorLi, Lijian
Recommended Citation
GB/T 7714
Zheng, Meisong,Wang, Zilong,Li, Lijian. DAO: Dual module redundancy with AND/OR logic voter[C],2015.
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