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DAO: Dual module redundancy with AND/OR logic voter
Zheng, Meisong; Wang, Zilong; Li, Lijian
2015-10
会议名称2015 ICRSE & PHM
会议录名称The First International Conference on Reliability Systems Engineering
会议日期2015-10-21
会议地点Beijing
摘要As device size shrinks, SRAM-based FPGAs are increasingly prone to be affected by single-event upsets (SEUs). SEU mitigation techniques for FPGAs are mostly expensive in terms of area and power costs. This paper proposes a new design for FPGA hardening using dual-modular redundancy (DMR). The duplication operates on lookup-table (LUT) level, and each pair of identical LUTs will be voted by an AND or OR logic voter. By virtue of the fault-masking effect of AND/OR logic, certain faults in duplicated LUTs will not propagate to the next level of the hardened circuit. Results on MCNC’91 benchmarks show that the proposed method can reduce 90% faults with an area overhead of 100% additional number of LUTs, and the runtime of the proposed algorithm is much shorter than other existing methods. 
关键词Fpga Fault Tolerance Dual Modular Redundancy Fault Sensitivity
收录类别EI
文献类型会议论文
条目标识符http://ir.ia.ac.cn/handle/173211/11745
专题空天信息研究中心
通讯作者Li, Lijian
作者单位中国科学院自动化研究所
推荐引用方式
GB/T 7714
Zheng, Meisong,Wang, Zilong,Li, Lijian. DAO: Dual module redundancy with AND/OR logic voter[C],2015.
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文件名: DAO Dual Module Redundancy with ANDOR Logic Voter for FPGA Hardening .pdf
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