Fault Injection Method and Voter Design for Dual Modual Redundancy FPGA Hardening

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	Fault Injection Method and Voter Design for Dual Modual Redundancy FPGA Hardening
	Zheng, Meisong; Wang, Zilong; Li, Lijian
	2016-06
会议名称	ICEIEC 2016
会议录名称	IEEE International Conference on Election Information and Emergency Communication
会议日期	2016-6-17
会议地点	Beijing
摘要	Hardware overhead and system reliability has always been in a dilemma in the world of FPGA designing. This paper provides a hardware overhead free dual modular redundancy (DMR) voter scheme using the abundant and unused carry chains in Xilinx FPGAs. And the experimental evaluation on MCNC benchmarks are carried on real FPGA and logic-simulation based fault injection method, respectively. Experimental results under the two methods are identical; hence validates the effectiveness of logic-simulation method and the DMR hardening scheme we have designed.
关键词	Fpga Fault Tolerance Fault Injection Redundancy
收录类别	EI
文献类型	会议论文
条目标识符	http://ir.ia.ac.cn/handle/173211/11749
专题	空天信息研究中心
通讯作者	Li, Lijian
作者单位	中国科学院自动化研究所
第一作者单位	中国科学院自动化研究所
通讯作者单位	中国科学院自动化研究所
推荐引用方式 GB/T 7714	Zheng, Meisong,Wang, Zilong,Li, Lijian. Fault Injection Method and Voter Design for Dual Modual Redundancy FPGA Hardening[C],2016.