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Fault Injection Method and Voter Design for Dual Modual Redundancy FPGA Hardening
Zheng, Meisong; Wang, Zilong; Li, Lijian
2016-06
Conference NameICEIEC 2016
Source PublicationIEEE International Conference on Election Information and Emergency Communication
Conference Date2016-6-17
Conference PlaceBeijing
AbstractHardware overhead and system reliability has always been in a dilemma in the world of FPGA designing. This paper provides a hardware overhead free dual modular redundancy (DMR) voter scheme using the abundant and unused carry chains in Xilinx FPGAs. And the experimental evaluation on MCNC benchmarks are carried on real FPGA and logic-simulation based fault injection method, respectively. Experimental results under the two methods are identical; hence validates the effectiveness of logic-simulation method and the DMR hardening scheme we have designed.   
KeywordFpga Fault Tolerance Fault Injection Redundancy
Indexed ByEI
Document Type会议论文
Identifierhttp://ir.ia.ac.cn/handle/173211/11749
Collection空天信息研究中心
Corresponding AuthorLi, Lijian
Affiliation中国科学院自动化研究所
Recommended Citation
GB/T 7714
Zheng, Meisong,Wang, Zilong,Li, Lijian. Fault Injection Method and Voter Design for Dual Modual Redundancy FPGA Hardening[C],2016.
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