As device size shrinks, SRAM-based FPGAs are increasingly prone to be affected by single-event upsets (SEUs). Triple module redundancy (TMR) hardening technique is the most effective and applicable method nowadays, but it is really expensive in terms of area and power costs. Selective TMR can greatly reduce the area overhead with a small loss of SEU immunity, hence in this work, we propose a new strategy for selective TMR based on don’t care configuration bits distribution. Don’t care configuration bits are calculated by means of windowing for each LUTs in the circuit, with the statistics of don’t care configuration bits, LUTs are classified into two sets: SEU-sensitive or SEU-insensitive. SEU-insensitive LUTs remain unchanged whereas SEU-sensitive LUTs have to be tripled and voted. The triplication operates on Look-up table (LUT) level, and each triplicated LUTs are voted by a voter built by the abundant tristate buffer (BUFT) resources in Virtex FPGAs, hence no area overhead will be brought in by voter insertion. Experiments on MCNC’91 benchmarks show that our method can reduce about 30% area overhead comparing with full TMR method, and the average failure rate reduced 4.5 times than original circuits. Our method made a good balance between area saving and reliability assurance, and can result in a very high SEU immunity along with the FPGA scrubbing technique.
; 王子龙
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