|关键词||Fpga Dsp Sift特征点 嵌入式系统 机器视觉 硬件计算|
|其他摘要||SIFT, short for Scale Invariant Feature Transform, is a well-known algorithm in computer vision for keypoint detection and matching, and has great application value in such fields as object recognition, stereo vision and so on. However, due to its high computational complexity, SIFT can hardly satisfy the requirements of real-time applications when implemented with pure software. This thesis accomplishes real-time computation of SIFT algorithm through hardware and parallel computing derived from the cooperation between an FPGA chip and a DSP chip which are embedded in an image gathering and processing card developed by our research team. The content of this thesis can be summarized as follows.|
(1) The keypoint detection and matching scheme in SIFT algorithm is analyzed in detail, together with the architecture of the image card. On this basis, an efficient implementation scheme is proposed for accelerating the entire SIFT algorithm through the cooperation of hardware computation and software computation which are implemented on an FPGA and a DSP respectively.
(2) After analyzing existing literature on detecting SIFT keypoints with FPGAs, this thesis points out a number of design flaws in those pioneering work, and proposes a new scheme for implementing SIFT keypoint detection on an FPGA. This new scheme adapts the original algorithm with a number of measures, such as adopting small Gaussian kernels to accomplish the same effect of expanding the image size, choosing scale levels properly to balance the amount and noise-robustness of keypoints, introducing a new method named ADIDER (Area Density Interpolation and Dual Extremum Restriction) in the keypoint detection procedure to improve the scale invariance of keypoints as well as raising the precision of fixed-point-number computation, and removing the step of “accurate localization of keypoints” in the original algorithm to facilitate pipelined implementation. These measures not only reduce the amount of computation, but also boost the robustness of SIFT keypoints. On this basis, a highly efficient hardware computation architecture is designed, making it possible to take enough bits in fixed-point numbers so as to guarantee the accuracy. Experimental results have demonstrated the effectiveness of the adaptations on the original algorithm and the validity of the hardware implementation structure.
(3) The underlying principles of extracting and matching the descriptors of SIFT keypoints is expounded, and a new algorithm adapted for the FPGA+DSP architecture is proposed based on a 72-dimensional descriptor. This new algorithm is highlighted by several improvements compared to the original algorithm. Firstly, by reducing the dimension of the descriptor from 128 to 72, memory space is saved and the computing effort in keypoint matching is cut down. Secondly, by employing a cone-shaped weighting function and a triangular membership function, the descriptors become more robust and can be matched correctly even under small change of the keypoint localization. Finally, by defining the distance between two descriptors with the ∞-norm instead of 2-norm (Euclidean distance), the computing time is reduced significantly. A hardware implementation scheme of this new algorithm is designed and realized, with the DSP invoking several pipelined FPGA modules which enhanced the computing speed through parallel computation.
(4) Two experiments have been conducted. In the first experiment, SIFT keypoints are used for the detection and differentiation of a number of model planes with different shapes and patterns. In the second experiment, a binocular vision system is built with SIFT keypoints from one camera matched to those from the other camera. The performance of the system in terms of both accuracy and speed have demonstrated the validity of the hardware implementation scheme proposed in this thesis for the detection and matching of SIFT keypoints.
|肖晗. 基于FPGA与DSP的SIFT特征点检测与匹配方法研究[D]. 北京. 中国科学院研究生院,2011.|