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基于FPGA与DSP的SIFT特征点检测与匹配方法研究
肖晗
学位类型工学博士
导师原魁
2011-05-27
学位授予单位中国科学院研究生院
学位授予地点北京
关键词Fpga Dsp Sift特征点 嵌入式系统 机器视觉 硬件计算
摘要SIFT算法是计算机视觉中一种著名的特征点检测与匹配算法,在目标识别、立体视觉等领域具有重要的应用价值。然而,SIFT算法的计算复杂度很高,用纯软件实现难以满足实时应用的需求。本文在课题组自行开发的图像采集处理卡上,通过FPGA与DSP的分工协作利用硬件并行方式实现了SIFT算法的实时计算。本文的工作可以概括如下:
1、在对本课题组图像采集处理卡的结构和工作原理进行理解和改进的基础上,结合硬件系统工作特点对SIFT特征点检测与匹配算法的原理进行了剖析,给出了利用FPGA和DSP技术实现SIFT算法的硬件和软件体系结构;
2、在对利用FPGA实现SIFT特征点检测的现有成果进行分析的基础上,结合硬件工作特点,对SIFT特征点检测算法进行了改进,其中包括:采用较小高斯滤波核等效代替图像增大运算以降低计算量;合理选择尺度层次以兼顾特征点的数量和抗噪声性能;采用“面双法”(面密度插值法和双重极值点约束)检测特征点以提高特征点的尺度不变性和定点数计算精度;取消极值点的“精确定位”以便于硬件实现。在硬件方面,设计了一种高效率的电路计算方案,该方案以更为合理的结构能够采用足够多的定点数位数,从而保证了计算精度。实验结果证明了算法改进和硬件实现的有效性。
3、对SIFT算法中的特征描述向量提取和匹配方法行了深入研究,面向FPGA+DSP实现提出了一种基于72维特征描述向量的改进算法:特征描述向量由128维降至72维,以节约存储空间,减少匹配计算量;合理运用锥形函数和三角隶属度函数进行加权,以提高描述向量对特征点位置偏移的鲁棒性;采用∞-范数定义描述向量的长度和距离,以减少计算时间。设计实现了一种通过DSP调用FPGA模块的实现方案,利用FPGA内的流水线结构实现改进算法的较大计算量,有效提高了计算速度。
4、分别以模型飞机识别问题和双目视觉中的特征点匹配问题为应用背景进行了实验,实验结果证实了本文所提基于FPGA和DSP技术的SIFT特征点检测和匹配实现方案的有效性、合理性和实用性。
其他摘要SIFT, short for Scale Invariant Feature Transform, is a well-known algorithm in computer vision for keypoint detection and matching, and has great application value in such fields as object recognition, stereo vision and so on. However, due to its high computational complexity, SIFT can hardly satisfy the requirements of real-time applications when implemented with pure software. This thesis accomplishes real-time computation of SIFT algorithm through hardware and parallel computing derived from the cooperation between an FPGA chip and a DSP chip which are embedded in an image gathering and processing card developed by our research team. The content of this thesis can be summarized as follows.
(1) The keypoint detection and matching scheme in SIFT algorithm is analyzed in detail, together with the architecture of the image card. On this basis, an efficient implementation scheme is proposed for accelerating the entire SIFT algorithm through the cooperation of hardware computation and software computation which are implemented on an FPGA and a DSP respectively.
(2) After analyzing existing literature on detecting SIFT keypoints with FPGAs, this thesis points out a number of design flaws in those pioneering work, and proposes a new scheme for implementing SIFT keypoint detection on an FPGA. This new scheme adapts the original algorithm with a number of measures, such as adopting small Gaussian kernels to accomplish the same effect of expanding the image size, choosing scale levels properly to balance the amount and noise-robustness of keypoints, introducing a new method named ADIDER (Area Density Interpolation and Dual Extremum Restriction) in the keypoint detection procedure to improve the scale invariance of keypoints as well as raising the precision of fixed-point-number computation, and removing the step of “accurate localization of keypoints” in the original algorithm to facilitate pipelined implementation. These measures not only reduce the amount of computation, but also boost the robustness of SIFT keypoints. On this basis, a highly efficient hardware computation architecture is designed, making it possible to take enough bits in fixed-point numbers so as to guarantee the accuracy. Experimental results have demonstrated the effectiveness of the adaptations on the original algorithm and the validity of the hardware implementation structure.
(3) The underlying principles of extracting and matching the descriptors of SIFT keypoints is expounded, and a new algorithm adapted for the FPGA+DSP architecture is proposed based on a 72-dimensional descriptor. This new algorithm is highlighted by several improvements compared to the original algorithm. Firstly, by reducing the dimension of the descriptor from 128 to 72, memory space is saved and the computing effort in keypoint matching is cut down. Secondly, by employing a cone-shaped weighting function and a triangular membership function, the descriptors become more robust and can be matched correctly even under small change of the keypoint localization. Finally, by defining the distance between two descriptors with the ∞-norm instead of 2-norm (Euclidean distance), the computing time is reduced significantly. A hardware implementation scheme of this new algorithm is designed and realized, with the DSP invoking several pipelined FPGA modules which enhanced the computing speed through parallel computation.
(4) Two experiments have been conducted. In the first experiment, SIFT keypoints are used for the detection and differentiation of a number of model planes with different shapes and patterns. In the second experiment, a binocular vision system is built with SIFT keypoints from one camera matched to those from the other camera. The performance of the system in terms of both accuracy and speed have demonstrated the validity of the hardware implementation scheme proposed in this thesis for the detection and matching of SIFT keypoints.
文献类型学位论文
条目标识符http://ir.ia.ac.cn/handle/173211/12131
专题毕业生_博士学位论文
作者单位中国科学院自动化研究所
推荐引用方式
GB/T 7714
肖晗. 基于FPGA与DSP的SIFT特征点检测与匹配方法研究[D]. 北京. 中国科学院研究生院,2011.
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