|肖晗; 何文浩; 原魁; 柴晓杰|
In order to achieve real-time detection of scale invariant feature transform (SIFT) keypoint via hardware circuits in field programmable gate array (FPGA), the original algorithm was ameliorated and a new method based on area density interpolation and dual extremum restriction was proposed, which can greatly enhance the scale invarience of SIFT keypoints while benefiting the computation accuracy of fixed-point numbers. After that, a highly efficient hardware computation scheme was designed and implemented in an FPGA chip with all the computational procedures arranged in a pipelined structure. Compared with existing research achievements, the above-mentioned scheme needs much less hardware resources, resulting in the great reduction of hardware costs and the great improvement of computation accuacy. The system can perform image acquisition and keypoint detection at the same time. For an image size of 360×288, its theoretical maximum throughput can reach 303 fps (frames per second), while its current actual processing rate is 25 fps because it is limited by the speed of the camera.
|Keyword||尺度不变特征变换(Sift) 现场可编程门阵列(Fpga) 特征点检测 机器视觉 硬件计算|
|肖晗,何文浩,原魁,等. 基于FPGA的SIFT特征点检测[J]. 高技术通讯,2012,22(4):429-435.|
|MLA||肖晗,et al."基于FPGA的SIFT特征点检测".高技术通讯 22.4(2012):429-435.|
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|2012_基于FPGA的SIFT特征点检（3646KB）||期刊论文||作者接受稿||开放获取||CC BY-NC-SA||View Download|
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