智能制造技术与系统研究中心知识库

In order to achieve real-time detection of scale invariant feature transform (SIFT) keypoint via hardware circuits in field programmable gate array (FPGA), the original algorithm was ameliorated and a new method based on area density interpolation and dual extremum restriction was proposed, which can greatly enhance the scale invarience of SIFT keypoints while benefiting the computation accuracy of fixed-point numbers. After that, a highly efficient hardware computation scheme was designed and implemented in an FPGA chip with all the computational procedures arranged in a pipelined structure. Compared with existing research achievements, the above-mentioned scheme needs much less hardware resources, resulting in the great reduction of hardware costs and the great improvement of computation accuacy. The system can perform image acquisition and keypoint detection at the same time. For an image size of 360×288, its theoretical maximum throughput can reach 303 fps (frames per second), while its current actual processing rate is 25 fps because it is limited by the speed of the camera.