A reconfigurable low-cost memory-efficient VLSI architecture for video scaling
Wang, Yangang; Peng, Silong,
2013
发表期刊High Technology Letters,
卷号19(2)期号:2013年02期页码:pp 137-144 (EI)
摘要A runtime reconfigurable very-large-scale integration(VLSI) architecture for image and video scaling by arbitrary factors with good antialiasing performance is presented in this paper.Video scaling is used in a wide range of applications from broadcast,medical imaging and high-resolution video effects to video surveillance,and video conferencing.Many algorithms have been proposed for these applications,such as piecewise polynomial kernels and windowed sine kernels.The sum of three shifted versions of a B-spline function,whose weights can be adjusted for different applications,is adopted as the main filter.The proposed algorithm is confirmed to be effective on image scaling applications and also verified by many widely acknowledged image quality measures.The reconfigurable hardware architecture constitutes an arbitrary scaler with low resource consumption and high performance targeted for field programmable gate array(FPGA) devices.The scaling factor can be changed on-the-fly,and the filter can also be changed during runtime within a unifying framework.
关键词Video Scaling / Very-large-scale Integration(Vlsi) Architecture / Polyphase Filter / Reconfiguration
文献类型期刊论文
条目标识符http://ir.ia.ac.cn/handle/173211/12959
专题智能制造技术与系统研究中心_多维数据分析
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GB/T 7714
Wang, Yangang,Peng, Silong,. A reconfigurable low-cost memory-efficient VLSI architecture for video scaling[J]. High Technology Letters,,2013,19(2)(2013年02期):pp 137-144 (EI).
APA Wang, Yangang,&Peng, Silong,.(2013).A reconfigurable low-cost memory-efficient VLSI architecture for video scaling.High Technology Letters,,19(2)(2013年02期),pp 137-144 (EI).
MLA Wang, Yangang,et al."A reconfigurable low-cost memory-efficient VLSI architecture for video scaling".High Technology Letters, 19(2).2013年02期(2013):pp 137-144 (EI).
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