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基于UVM的协同仿真硬件加速验证平台的研究与实现
李品
学位类型工程硕士
导师胡绍勇
2017-05-25
学位授予单位中国科学院研究生院
学位授予地点北京
关键词硬件加速器 Uvm 硬件协同仿真 基于事务的加速 验证平台
其他摘要
       集成电路技术与工艺日新月异,设计规模不断增大,复杂度越来越高,但是验证方法和工具的发展与设计规模和复杂度的提升并不匹配,验证面临着巨大的挑战。一般在集成电路设计的开发过程中,验证约占工程开发总投入的50%~70%,几乎伴随了集成电路设计的整个开发过程,可见验证已经成为集成电路设计的一大瓶颈。
       传统的基于模拟的软件验证是功能验证的主要方法之一,但是随着RTL设计规模和复杂度的提升,基于模拟的动态验证方法其验证速度下降,会延长整个验证周期。形式化验证是功能验证中增长最快的方法之一,但是受到专业知识或应用范围的限制,仍然不能解决目前验证面临的诸多困难。传统的支持硬件的验证工具可以提升验证性能,但是将整个验证平台以及DUT移植到硬件上,使新的验证平台完全脱离了原来工作站上的软件模拟环境,其可调试性和可重用性差,并且不利于生成大量的测试用例。
     本文立足于验证技术和验证方法发展现状,采用硬件加速技术,结合目前主流验证语言SystemVerilog以及验证方法学UVM搭建一个可重用性强、性能较好的UVMA协同仿真验证平台。该平台使用硬件加速器Palladium XP,将待测电路和满足AXI协议的接口移植到硬件加速器上,平台的其余部分仍然运行在软件模拟器上,既利用了硬件加速器的加速特性获得性能提升又保持了软件端的灵活性可生成大量测试激励代码。平台采用基于事务的加速-TBA技术,把验证从信号级抽象到更高的事务级,可快速地开发新的复杂的测试,方便用户创建和重用验证平台,简化代码,并有助于模拟运行调试和覆盖率分析,同时也提高了工作效率。本文深入研究UVM验证方法学,应用UVM验证平台开发框架,搭建一个基于UVM的高可重用加速验证平台,缩短验证周期,提高验证效率。
     本文设计的验证平台针对中科院自动化研究所集成中心的第二代代数处理器(UCP、HPP、UMP),运用该UVM加速验证平台完成处理器内核APE的验证。实验结果表明,与基于模拟的软件验证平台相比,该平台速度更快,性能好;与基于Palladium的ICE模式验证平台相比,该平台更灵活、可重用性好,可实时生成测试激励。简而言之,该验证平台缩短验证周期,性能较好,可重用性高。
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      As integrated circuit technology and process blooming with each passing day, the scale of IC design is increasing and complexity is getting higher. However, the development of verification methods and tools do not match the growth of design scale and complexity, which makes IC verification confront tough challenges.Generally in the process of IC projects development, the average time spent in verification accounts for about 50% to 70% of total project time. That is to say, verification almost accompanies the entire process of IC projects development. In short, verification has become a major bottleneck in IC design.
    The traditional simulation-based verification is one of the important methods of functional verification. With the increase in design scale and complexity, the performance of verification declines using traditional methods, which leads to more verification cycles. Formal verification is one of the fastest growing methods in functional verification, but it requires expertise or is limited by the scope of adoption. It still does not address many of the challenges that verification currently faces. Although the traditional hardware emulation-based verification method, which maps the entire testbench including DUT on the emulator, can improve the verification performance the new verification environment is completely separated from the software simulation environment on workstation, which makes debugging difficult and reusability poor. In addition, the traditional hardware verification method is not conducive to generate a large number of test cases.
    Based on the requirements of participating projects and development of verification technoloogy, this paper uses hardware acceleration technology to build a Co-emulation and UVM-based accelerated verification platform that is reusable and obtains high performance. It utilizes the current mainstream verification language and method. The testbench applies the hardware emulator-Palladium XP, mapping the DUT and the AXI protocol interface on the hardware accelerator. The rest of the testbench is still mapped on the software simulator. On one hand, the platform uses the hardware accelerator to accelerate the verification and increase run time performance.On the other hand, it maintains the flexibility of software simulation and can generate a large number of test cases. This testbench introduces transaction-based acceleration (TBA) technology to extract verification from the signal level to a higher transaction level without consideration of some detailed information. So we can rapidly develop some new complex cases. This technology is convenient to create and reuse the testbench. Moreover, it makes for simplifying code, simulation run-time debugging and coverage analysis, while also improving productivity. In this paper, we research UVM, and apply the UVM development framework of testbench to build a highly reusable UVM-based accelerated testbench. What is more, we can achieve shorter development cycle.
   The testbench in this paper is designed for the second generation mathematical processors (UCP, HPP, UMP) of Institute of Automation, Chinese Academy of Sciences. The core-APE in the mathematical processors is the DUT. The experimental results show that the testbench is much faster than the simulation-based testbench. Compared with the Palladium-based ICE emulation testbench, it is more flexible and reusable, and can generate test code in real time. In short, the testbench can shorten the verification cycle and obtain the strong reusability ang high performance.
文献类型学位论文
条目标识符http://ir.ia.ac.cn/handle/173211/14637
专题毕业生_硕士学位论文
作者单位中科院自动化研究所
推荐引用方式
GB/T 7714
李品. 基于UVM的协同仿真硬件加速验证平台的研究与实现[D]. 北京. 中国科学院研究生院,2017.
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