|Place of Conferral||北京|
|Keyword||硬件加速器 Uvm 硬件协同仿真 基于事务的加速 验证平台|
As integrated circuit technology and process blooming with each passing day, the scale of IC design is increasing and complexity is getting higher. However, the development of verification methods and tools do not match the growth of design scale and complexity, which makes IC verification confront tough challenges.Generally in the process of IC projects development, the average time spent in verification accounts for about 50% to 70% of total project time. That is to say, verification almost accompanies the entire process of IC projects development. In short, verification has become a major bottleneck in IC design.
The traditional simulation-based verification is one of the important methods of functional verification. With the increase in design scale and complexity, the performance of verification declines using traditional methods, which leads to more verification cycles. Formal verification is one of the fastest growing methods in functional verification, but it requires expertise or is limited by the scope of adoption. It still does not address many of the challenges that verification currently faces. Although the traditional hardware emulation-based verification method, which maps the entire testbench including DUT on the emulator, can improve the verification performance the new verification environment is completely separated from the software simulation environment on workstation, which makes debugging difficult and reusability poor. In addition, the traditional hardware verification method is not conducive to generate a large number of test cases.
Based on the requirements of participating projects and development of verification technoloogy, this paper uses hardware acceleration technology to build a Co-emulation and UVM-based accelerated verification platform that is reusable and obtains high performance. It utilizes the current mainstream verification language and method. The testbench applies the hardware emulator-Palladium XP, mapping the DUT and the AXI protocol interface on the hardware accelerator. The rest of the testbench is still mapped on the software simulator. On one hand, the platform uses the hardware accelerator to accelerate the verification and increase run time performance.On the other hand, it maintains the flexibility of software simulation and can generate a large number of test cases. This testbench introduces transaction-based acceleration (TBA) technology to extract verification from the signal level to a higher transaction level without consideration of some detailed information. So we can rapidly develop some new complex cases. This technology is convenient to create and reuse the testbench. Moreover, it makes for simplifying code, simulation run-time debugging and coverage analysis, while also improving productivity. In this paper, we research UVM, and apply the UVM development framework of testbench to build a highly reusable UVM-based accelerated testbench. What is more, we can achieve shorter development cycle.
The testbench in this paper is designed for the second generation mathematical processors (UCP, HPP, UMP) of Institute of Automation, Chinese Academy of Sciences. The core-APE in the mathematical processors is the DUT. The experimental results show that the testbench is much faster than the simulation-based testbench. Compared with the Palladium-based ICE emulation testbench, it is more flexible and reusable, and can generate test code in real time. In short, the testbench can shorten the verification cycle and obtain the strong reusability ang high performance.
|李品. 基于UVM的协同仿真硬件加速验证平台的研究与实现[D]. 北京. 中国科学院研究生院,2017.|
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