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基于FPGA的MaPU原型验证平台的设计与研究
郭芳金
学位类型工程硕士
导师马小军
2017-05
学位授予单位中国科学院研究生院
学位授予地点北京
关键词Fpga原型验证 Mapu 层次聚类 逻辑分割算法
其他摘要       随着SoC设计规模的不断增长,验证工作变得越来越重要。据Mentor Graphic公司统计,验证和调试所花费的时间占整个项目时间的46%以上。传统基于软件模拟的验证仿真速度慢,已无法满足当前的验证需求。为了缩短验证时间,基于FPGA的原型验证已成为SoC验证的重要手段。FPGA原型验证具有速度快、成本低和运行在真实硬件环境的优势,能够有效缩短项目时间,加快产品上市。
       本文致力于研究基于FPGA的原型验证平台,以实现对MaPU(Mathematics Process Unit)系列处理器的功能验证。首先,简要分析了目前常用的验证技术并对比了其各自的优缺点。接着,详细阐述了如何搭建一个完备的FPGA原型验证平台,并对其中的每一个环节进行了简要说明。最后,结合MaPU系列处理器的特点,研究了可重用原型验证平台的设计与多FPGA系统的逻辑分割算法。
       为了满足原型平台需要在多个项目中重复使用的验证需求,提出了基于FPGA的可重用原型验证平台。结合目前主流的IP复用技术,本文将可重用性引入到原型验证过程中,并详细讨论了如何利用可重用性来提高验证效率。在此基础上,本文重点分析了MaPU系列处理器的可重用性。在Synopsys HAPS70-S24器件上实现了MaPU原型验证平台,在该平台上验证了ARM读写DDR3的程序。
       为了解决大规模SoC设计无法完全映射到单片FPGA上的问题,本文研究了逻辑分割算法。目前已有的两类逻辑分割算法(综合前分割、综合后分割)都存在不同的缺陷,为了进一步提高分割效率,本文对传统的模块分割算法进行了改进,提出了基于层次聚类的模块分割算法。在多FPGA原型系统中,板间信号互联数目往往成为系统性能瓶颈,层次聚类算法能够根据距离矩阵最优化模块之间的互联信号数目。通过脚本程序提取模块的互联信号信息来构造距离矩阵,然后利用层次聚类算法来进行模块聚类,从而得到整个逻辑分割方案。基于层次聚类的模块分割算法能够在一定程度上克服综合前分割的盲目性,同时改善综合后分割速度慢的缺陷。为了确保算法的有效性,本文将基于层次聚类的模块分割算法应用到MaPU系列处理器的一个APE(Algebraic Processing Engine)核的分割过程中。实验结果表明,与Synopsys Certify的快速分割技术QPT相比,该算法具有更好的优化效果,可以将板间的信号互连数目减少23.62%。;        As the scale of SoC design continues to increase, verification has become more and more important. According to Mentor Graphic, the time spent on verification and debugging accounts for more than 46% of the whole project time. The traditional simulation based on software is slow and cannot meet the current verification requirements. In order to shorten the verification time, FPGA-based prototyping has become an important method of SoC verification. FPGA-based prototyping with fast, low cost and running in the real hardware, can significantly shorten the project time, speed up the product first to market.
       This paper focused on FPGA-based prototyping methodology in order to implement the functional verification platform of the MaPU (Mathematics Process Unit) series processors. First of all, we briefly analyze the most frequently use verification techniques and compare their advantages and disadvantages. Then, we elaborated on how to build a complete FPGA-based prototyping, and a brief description of each of step. Finally, in this paper we studied the design of reusable FPGA-based prototype verification platform and the logical partition algorithm of multi-FPGA system according to the feature of MaPU series processor.
       In order to meet the requirement that FPGA-based prototyping needs to be reused in multiple projects, a reusable prototype verification platform is proposed. With reference to the current mainstream IP reuse technology, this paper introduces reusability into the prototype verification and discusses how to use it to improve the verification efficiency. On this basis, this paper laid special stress on analyzing the reusability of MaPU series processors. FPGA-based prototyping of MaPU is implemented on the Synopsys HAPS70-S24 device, and the program of ARM read/write DDR3 is verified on this platform.
       In order to solve the problem that large-scale SoC design cannot be completely mapped to single FPGA, this paper studies the logical partition algorithm. The existing two categories of logical partition algorithm (pre-synthesis partition, post-synthesis partition) have different defects. To get more efficient algorithm, this paper improves the traditional module-based logical partition algorithm and propose a new logical partition algorithm based on hierarchical clustering. In multi-FPGA prototype systems, the number of inter-board signal interconnections is often a system performance bottlenecks, and the hierarchical clustering algorithm can optimize the number of interconnected signals according to the distance matrix of the module. By analyzing the RTL code through the script, we can get the interconnect information between modules. The distance matrix is constructed by the interconnection information, and then the hierarchical clustering algorithm is used to cluster modules. Therefore, we get the whole logical partition scheme. The partition algorithm based on hierarchical clustering can overcome the blindness of pre-synthesis partition to a certain extent and improve the defects of post-synthesis speed. In order to ensure the validity of the algorithm, we apply it to the partition process of an APE (Algebraic Processing Engine) kernel. The experimental results show that compared with the Synopsys Certify QPT (Quick Partition Technique), the algorithm has better optimization effect and can reduce the number of signal interconnections between boards by 23.62%.
文献类型学位论文
条目标识符http://ir.ia.ac.cn/handle/173211/14650
专题毕业生_硕士学位论文
作者单位国家专用集成电路设计工程技术研究中心
推荐引用方式
GB/T 7714
郭芳金. 基于FPGA的MaPU原型验证平台的设计与研究[D]. 北京. 中国科学院研究生院,2017.
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