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    信息化的现代战争需求军用智能装备的快速发展，其中军用雷达、遥感、声呐、通信等数字信号处理系统的升级，对数字信号处理器（DSP）的性能提出了更高的需求，而“陆海空天”四维一体化的情报网络需求更需要DSP具有军品级和宇航级的可靠性以适应不同的应用环境。当前在役的武器装备所采用的主流DSP是基于某指令集的架构的DSP，该DSP已经在大量核心武器装备中使用，为了这些装备的快速增量式发展、保证装备的一致性和可靠性以及降低装备研发和长期维护过程中的成本，需要下一代装备中所使用的DSP指令集向前兼容。但是当前使用该指令集的DSP性能和功能已渐渐无法满足下一代军用装备的需求，所以迫切需要一款兼容该指令集并具有更高的性能和更强的功能的DSP。本文正是基于军方这迫切需求，在“核高基”、“型谱”等多个军方项目的支持下，对加强型DSP的体系结构、处理器核高效控制器结构、运算器的优化算法以及宇航级处理器的加固方法进行了深入的研究，并取得了以下研究成果：

1. 提出一种面向军事应用的加强型DSP体系结构。该结构基于当前国防装备中大量应用的DSP指令集，根据下一代武器装备的需求进行研究与设计。与当前装备的主流DSP相比，该结构增加了200%的IO吞吐率、220%的外部访存带宽；拥有更优秀的程序控制器与运算单元实现算法；拥有更快速的内部存储响应能力，大大提高程序运行时指令与数据供给能力。经过评测，处理器综合性能至少提高了一倍。本项目完成之后可使用该自主设计的军品级芯片代替原进口工业级芯片，提高武器系统的可靠性，其更高的高性能并具有高速通用通信接口等特点使其在国防领域具有更广泛的应用前景。
2. 提出一种可降低冗余操作的DSP程序控制结构。在该控制结构中，使用一种可减少异步中断冗余握手的中断申请方法，相比通用方法，本方法在中断申请阶段可减少76.47%的时间；使用一种可降低冗余执行的分支指令调度方法，该方法可降低分支预测失败时冗余执行的指令数，根据分支类型的不同，可降低50%-83.33%分支预测失败开销。经过评测，本DSP控制结构可提高22%的中断响应速度，并在预测命中率为50%的情况下，降低25%-37%的分支指令执行时间。
3. 提出一种32位可重构高速定点乘累加器的结构。针对可重构定点乘累加器的多处关键逻辑，本文使用了多种创新性的实现方法：一种无延时开销的重构方法，支持整数/小数、累加/累减的快速重构；一种基于前导0/1的整数乘累加结果位宽控制方法，可降低30%的整数结果位宽控制时间；一种基于并行预判算法的小数乘累加舍入方法，与当前成熟方法相比，在降低12%延时的基础上，在面积上也有优势。综合结果表明，相比成熟结构，本文提出的结构可降低20%的延时，相比于使用动态电路且定制实现的乘累加器，本设计可至少提高10%的性能。
4. 提出一种针对深亚微米和纳米级工艺处理器的加固方法。随着工艺尺寸的降低，当前一些成熟的加固方案已经无法满足当前宇航级高性能处理器的加固要求，本文提出的加固方法创新性的根据流水级路径松弛程度决定加固方式，而且在动态功耗控制、版图布局及时钟树的设计等方面均给出了加固方案，并将这些解决方案形成了易于嵌入当前ASIC设计的加固流程。与成熟的同类方案相比，本方案性能损耗低、可靠性高且动态功耗低。后端结果表明，相对于成熟方案使用高性能单元库对内核进行加固，本方案使用低性能低功耗的单元库仍可得到相同性能，并可降低40%面积，63%功耗。当前使用该方案加固的DSP已经在兰州进行了重离子单粒子实验，结果初步表明该DSP的抗单粒子辐照能力优于军方要求指标。

    Information technology based modern warfare requires rapid development of military intelligent equipment. The evolution of military signal processing system of radar, remote sensing, sonar and communication demands higher performance of digital signal processor (DSP), and information network in land, sea, air and aerospace require more stability of DSP, especially in space applications. The mainstream DSPs used in key weapons and equipment in service are based on a certain instruction set. The DSP used in next generation equipment should be backward compatible for the sake of rapid incremental development, compatibility and stability of equipment. Also it can cut the cost of research, development and maintaining over the long lifecycle of all equipment. But available and compatible DSPs gradually cannot meet the requirements in performance and functions, so a new DSP is on the urgent demand. In order to satisfy that demand, this thesis conducts in-depth research on these issues with support of several national and ministerial projects: enhanced DSP architecture, efficient controller of DSP core, optimized structure of arithmetic units and radiation hardened technique in aerospace processor. This thesis has made the following achievements:

1. An enhanced DSP architecture for military applications is proposed. This architecture is based on the mainstream DSP instruction set used in Defense and designed to fulfill the demand of next generation weapon and equipment. Compared with the mainstream DSP currently used, this work has 200% more IO throughput and 220% more main memory access bandwidth. The processor core of this work has more efficient controller and higher optimized arithmetic units. And the memory system is built for more rapid response capability, supplying instructions and data more efficiently. The evaluation shows that this DSP architecture can achieve at least double performance. This military-rated DSP can replace the imported industrial DSP after tape-out and makes weapons and equipment more stable. Furthermore, because of the higher performance and general high-speed serial interfaces, this DSP has broad prospects in defense applications.
2. A more efficient structure of program controller in DSP core is proposed. In this work, a communication method that can reduce hand-shaking between interrupt controller and core is used. Compared with usual one, this method can reduce 76.74% time of interrupt request. Also, this work proposes a branch scheduling method that can reduce execution of redundant instructions if branch prediction fail. The method can reduce 50%-83.33% overhead of failure prediction, varying by the type of branches. Evaluation shows that, this controller can improve 22% speed when responding to an interrupt and consume 25%-37% less time of branch execution in case of 50% prediction accuracy.
3. A high performance reconfigurable 32-bit fixed multiply-accumulator (MAC) is proposed. Novel methods have been implemented in this work. Firstly, a performance lossless reconfigurable method is proposed to reconfigure from integer MAC to fraction MAC and from add-accumulation to sub-accumulation. Secondly, an extraction method from integer MAC result based on leading ones prediction is proposed, reducing 30% delay of extraction. Thirdly, a round method of fraction MAC result is proposed. Compared with the round method used in mature float multiplier, this method can not only reduce 12% delay but also take up less area. As a result of all three novel methods, this work cuts 20% path delay compared with the mature MAC according to the synthesis result, and this work can make 10% more performance compared with the MAC designed under full customer flow and implemented on dynamic CMOS units.
4. A novel processor hardened approach at normal deep-sub-micron and nanometers bulk-silicon process (PHOENIX) is proposed. As the shrinking scale of the process, current hardened technique cannot continue to use in high performance processor. PHOENIX innovatively varies registers’ protecting structure according to the slack of paths and offers a better solution on dynamic power control, placement of components and design of clock tree. All these solutions are easy to embed into mature ASIC design flow. Compared with the mature approach, PHOENIX consumes less performance and power and offers higher reliability. Backend evaluation shows that, PHOENIX can not only achieve the same performance when hardening the processor core based on lower performance and lower power standard cell library, but also lead to 40% less area and 63% less power. DSPs hardened by PHOENIX have been taped-out and conducted experiment of single event effects (SEE) induced by heavy ions in Lanzhou. The experiment preliminarily indicate that the DSP hardened by PHOENIX has better ability of anti-SEE than the requirement of this military project.