CASIA OpenIR  > 国家专用集成电路设计工程技术研究中心
A High Performance Multi-standard Viterbi Decoder
Zhao, Xuying1; Li, Huan1; Wang, Xiaoqin2
2017-10
Conference NameIEEE 7th International Conference on Electronics Information and Emergency Communication (ICEIEC 2017)
Pages1-4
Conference DateJuly 21-23, 2017
Conference PlaceShenzhen, China
AbstractConvolutional encoder is widelyapplied in lots
of wireless communication standards including 3G/4G mobile
communications, DVB (Digital Video Broadcasting),
IoT(Internet of Things) transmissions and so on. Therefore
multi-standard Viterbi decoder design for the above receivers
is a hot issue. In this paper, a reconfigurable high performance
Viterbi decoder design is proposed for LTE, WiMAX,
CDMA2000, GSM and TD-SCDMA. The proposed flexible
architecture supports polynomial reconfiguration, constraint
length of 5~9, and code rate of 1/2, 1/3, 1/4. Moreover, both
tail-biting and zero trellis terminating modes are supported.
To reduce decoding latency and complexity, it employs the
forward traceback method and sliding window pipeline
technology. Simulation results show that its maximum
decoding throughput is 1.15Gbps under a clock frequency of
600MHz. Finally, its area is about 0.2mm
2, and the power
consumption is about 46 mw, which is estimated with Synopsis
DC and TSMC 28nm standard cell library.

KeywordViterbi Decoder Multi-standard High Performance Forward Traceback Sliding Window
Document Type会议论文
Identifierhttp://ir.ia.ac.cn/handle/173211/15520
Collection国家专用集成电路设计工程技术研究中心
Corresponding AuthorZhao, Xuying
Affiliation1.中国科学院大学
2.中国科学院自动化研究所
Recommended Citation
GB/T 7714
Zhao, Xuying,Li, Huan,Wang, Xiaoqin. A High Performance Multi-standard Viterbi Decoder[C],2017:1-4.
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