高性能处理器中运算单元的研究与设计

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	高性能处理器中运算单元的研究与设计
	冯静
	2018-05
学位类型	工学硕士
英文摘要	运算单元是高性能处理器芯片中的关键部件，在视频图像处理、无线通信、超算等领域，由于数据量并行性高，对数据运算的精度和实时性要求高，而且这些数据的处理中有大部分的加法操作和乘法操作，对运算部件的运算性能提出了很高的要求，这是评价DSP性能的一个重要方面。本文依托中国科学院自动化研究所国家专用集成电路设计工程技术研究中心自主研制的高性能代数处理器“MaPU”的第二代处理器UCP,旨在研究和设计其中的运算部件，满足处理器对SIMD乘法运算和浮点运算处理能力的要求。本文设计的SIMD定点乘法器支持的数据粒度有word、short、byte类型，即乘法单元内部支持1个32x32-bit，2个16x16-bit或者4个8x8-bit的有符号/无符号乘法操作，1个16x16-bit或者2个8x8-bit的复数乘法操作。本文对加法器结构、乘法器算法和结构以及浮点运算单元做了深入的研究。乘法器实现的关键在于乘法运算中部分积的产生和部分积的累加电路的复杂度。本文采用改进的并行可复用多粒度的Booth编码算法来减少部分积的数目，采用3-2压缩器和4-2压缩器混合Wallace树型结构来加快压缩过程，并提出一种全新的硬件自动优化推导的方法。浮点运算能力是考察处理器性能的另一重要指标。本文设计的浮点乘法器支持单精度浮点和双精度浮点乘法，在具体设计中，进行符号位的处理，指数相加运算和尾数相乘运算，并对尾数进行规格化处理和舍入处理。在设计完成后进行经过功能验证，确保了验证的充分性和设计的正确性。利用Design Complier工具对设计进行逻辑综合，使得运算部件在28nmCMOS工艺下工作频率达到1.2GHz，达到所要求的的性能指标。 ; The computing unit is a key component of high performance processor chip, in the field of video image processing and wireless communications. For the requirements of the data parallelism, high precision and real-time operations of data, the processor should support the addition operation and multiplication operations. So it puts forward a very high demand on the capability of arithmetic unit, which is an important aspect to evaluate the performance of DSP. This project bases on the high-performance self-developed algebra processor "MaPU", from the National ASIC Design Engineering Center in Institute of Automation, Chinese Academy of Sciences. The second generation called UCP processor, aims at researching and designing computing components, to meet the SIMD multiplication and floating-point processing requirements. The SIMD multiplier designed in this paper supports multiple data granularities, such as word, short and byte type. The internal multiplication unit support can perform one 32x32, two 16x16, or four 8x8bit unsigned/signed multiplication, or one 16x16, or two 8x8bit complex number multiplication. This paper makes a thorough research on the structure of adder, the structure and algorithm of and multiplier, floating-point unit. The complexity of the multiplier lies in the generation and accumulation of the partial product. This paper adopts Booth encoding algorithm which is parallel multiple granularity, reducing the number of partial products. The Wallace tree structure mixed 3-2, and 4-2 compressor accelerates the accumulation process. What’s more, the paper puts forward a new method for automatic derivation optimization of hardware. Floating point capability is another important index to evaluate the performance of processor. The floating-point multiplier supports single precision floating-point and double precision floating-point multiplication. In the specific design, processing symbol, index arithmetic sum and mantissa multiplication are considered, and the standard of the processing and processing of the mantissa rounding also are handled. After the design is completed, we should verify the design to ensure the correctness and sufficiency of the validation. The logic synthesis of the design uses Design Complier tool. The operation component is implemented with 28nm CMOS process. The frequency of 1.2GHz achieves the requirement performance target.
关键词	乘法单元 Simd 浮点验证综合
语种	中文
文献类型	学位论文
条目标识符	http://ir.ia.ac.cn/handle/173211/21067
专题	毕业生_硕士学位论文
作者单位	中国科学院自动化研究所
第一作者单位	中国科学院自动化研究所
推荐引用方式 GB/T 7714	冯静. 高性能处理器中运算单元的研究与设计[D]. 北京. 中国科学院大学,2018.

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高性能处理器中运算单元的研究与设计.pd（2051KB）	学位论文		限制开放	CC BY-NC-SA