CASIA OpenIR  > 毕业生  > 硕士学位论文
Thesis Advisor马小军
Degree Grantor中国科学院大学
Place of Conferral北京
Keyword乘法单元 Simd 浮点 验证 综合
Other Abstract





在设计完成后进行经过功能验证,确保了验证的充分性和设计的正确性。利用Design Complier工具对设计进行逻辑综合,使得运算部件在28nmCMOS工艺下工作频率达到1.2GHz,达到所要求的的性能指标。

; The computing unit is a key component of high performance processor chip, in the field of video image processing and wireless communications. For the requirements of the data parallelism, high precision and real-time operations of data, the processor should support the addition operation and multiplication operations. So it puts forward a very high demand on the capability of arithmetic unit, which is an important aspect to evaluate the performance of DSP.
This project bases on the high-performance self-developed algebra processor "MaPU", from the National ASIC Design Engineering Center in Institute of Automation, Chinese Academy of Sciences. The second generation called UCP processor, aims at researching and designing computing components, to meet the SIMD multiplication and floating-point processing requirements.
The SIMD multiplier designed in this paper supports multiple data granularities, such as word, short and byte type. The internal multiplication unit support can perform one 32x32, two 16x16, or four 8x8bit unsigned/signed multiplication, or one 16x16, or two 8x8bit complex number multiplication. This paper makes a thorough research on the structure of adder, the structure and algorithm of and multiplier, floating-point unit. The complexity of the multiplier lies in the generation and accumulation of the partial product. This paper adopts Booth encoding algorithm which is parallel multiple granularity, reducing the number of partial products. The Wallace tree structure mixed 3-2, and 4-2 compressor accelerates the accumulation process. What’s more, the paper puts forward a new method for automatic derivation optimization of hardware.
Floating point capability is another important index to evaluate the performance of processor. The floating-point multiplier supports single precision floating-point and double precision floating-point multiplication. In the specific design, processing symbol, index arithmetic sum and mantissa multiplication are considered, and the standard of the processing and processing of the mantissa rounding also are handled.
After the design is completed, we should verify the design to ensure the correctness and sufficiency of the validation. The logic synthesis of the design uses Design Complier tool. The operation component is implemented with 28nm CMOS process. The frequency of 1.2GHz achieves the requirement performance target.

Document Type学位论文
First Author AffilicationInstitute of Automation, Chinese Academy of Sciences
Recommended Citation
GB/T 7714
冯静. 高性能处理器中运算单元的研究与设计[D]. 北京. 中国科学院大学,2018.
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