A bypass-based low latency network-on-chip router
Guo, Peng1,2; Liu, Qingbin1,2; Chen, Ruizhi1,2; Yang, Lei1; Wang, Donglin1
Corresponding AuthorGuo, Peng(
AbstractAs the most critical components of Network on chip (NoC), the routers need to select suitable output ports and guarantee every flit accesses the hardware resource exclusively. Thus they are normally designed with several pipelines. However, most flits don't compete for the same output port with other flits in real applications. In this work, we introduce a bypass path to the traditional router thus the non-conflict flits can be forwarded directly. Combined with several other optimizations, we propose a bypass-based low latency NoC router (BNR). When no congestion occurs, BNR can transfer the flit through the bypass path with only one cycle. Otherwise, the flits are transferred through the conventional path with two hops. Besides, we also present a simplified version, BNR-S. Compared with BNR, it only bypasses the short packets and will reduce the area overhead significantly. For the synthetic traffic with different injection rate, BNR achieves 1.48x and 1.31x speedup than the two baselines while BNR-S achieves 1.3x and 1.15x. They also bring obvious benefits for several real applications. In addition, the experiments also illustrate that the proposed bypass mechanism can reduce dynamic power.
Keywordnetwork-on-chip router bypass low latency
Indexed BySCI
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000462020400011
Citation statistics
Cited Times:2[WOS]   [WOS Record]     [Related Records in WOS]
Document Type期刊论文
Corresponding AuthorGuo, Peng
Affiliation1.Chinese Acad Sci, Inst Automat, Beijing, Peoples R China
2.Univ Chinese Acad Sci, Beijing, Peoples R China
First Author AffilicationInstitute of Automation, Chinese Academy of Sciences
Corresponding Author AffilicationInstitute of Automation, Chinese Academy of Sciences
Recommended Citation
GB/T 7714
Guo, Peng,Liu, Qingbin,Chen, Ruizhi,et al. A bypass-based low latency network-on-chip router[J]. IEICE ELECTRONICS EXPRESS,2019,16(4):12.
APA Guo, Peng,Liu, Qingbin,Chen, Ruizhi,Yang, Lei,&Wang, Donglin.(2019).A bypass-based low latency network-on-chip router.IEICE ELECTRONICS EXPRESS,16(4),12.
MLA Guo, Peng,et al."A bypass-based low latency network-on-chip router".IEICE ELECTRONICS EXPRESS 16.4(2019):12.
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