CASIA OpenIR  > 国家专用集成电路设计工程技术研究中心
A Distributed Register File Architecture Based on Dynamic Scheduling for VLIW Machine
Yang Guo1,2; Donglin Wang1; Zijun Liu1; Hongyu Meng1,2
2018-06
Conference NameInternational Conference on Electronics Information and Emergency Communication.
Conference Date2018-6
Conference Place北京
Abstract

Distributed register files have the advantages of area and power compared with centralized register files in very long instruction word (VLIW) machine. But it may complicate the internetwork. A distributed register file architecture based on dynamic scheduling is proposed in our work. A portion of latency on internetwork is shifted to the latency among registers by latency transfer. And the decrease in the fanout of writing ports leads to a reduction in the power of the internetwork. To ensure the external compatibility of the distributed register file interface, the register was redirection designed. A dynamic scheduling strategy is designed to avoid conflicts between physical entities and logical entities that redirect registers. The optimization was evaluated on our in-house processor. The register file based on distributed dynamic scheduling reduces 15.48% of latency. The system frequency is raised from 1.19 GHz to 1.41 GHz. The power decreased by 27.42%.

Language英语
Document Type会议论文
Identifierhttp://ir.ia.ac.cn/handle/173211/23706
Collection国家专用集成电路设计工程技术研究中心
Affiliation1.Institute of Automation, Chinese Academy of Sciences (CASIA), Beijing, China
2.University of Chinese Academy of Sciences (UCAS), Beijing, China
First Author AffilicationInstitute of Automation, Chinese Academy of Sciences
Recommended Citation
GB/T 7714
Yang Guo,Donglin Wang,Zijun Liu,et al. A Distributed Register File Architecture Based on Dynamic Scheduling for VLIW Machine[C],2018.
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