CASIA OpenIR  > 国家专用集成电路设计工程技术研究中心
A High-Efficiency FPGA-Based Accelerator for Binarized Neural Network
Guo Peng1,2; Ma Hong1; Ruizhi Chen1,2; Donglin Wang1
Source PublicationJournal of Circuits, Systems, and Computers
2019-04
Volume28Issue:1Pages:1
Abstract

Although the convolutional neural network (CNN) has exhibited outstanding performance in various applications, the deployment of CNN on embedded and mobile devices
is limited by the massive computations and memory footprint. To address these challenges, Courbariaux and Bengio put forward binarized neural network (BNN) which
quantizes the weights and activations to ±1. From the perspective of hardware, BNN
can greatly simplify the computation and reduce the storage. In this work, we first
present the algorithm optimizations to further binarize the first layer and the padding
bits of BNN; then we propose a fully binarized CNN accelerator. With the ShuffleCompute structure and the memory-aware computation schedule scheme, the proposed
design can boost the performance for feature maps of different sizes and make full use
of the memory bandwidth. To evaluate our design, we implement the accelerator on
the Zynq ZC702 board, and the experiments on the SVHN and Cifar10 datasets show
state-of-the-art performance-efficiency and resource-efficiency
 

KeywordCnn Bnn Fpga Accelerator
Indexed BySCI
Document Type期刊论文
Identifierhttp://ir.ia.ac.cn/handle/173211/23878
Collection国家专用集成电路设计工程技术研究中心
Corresponding AuthorGuo Peng
Affiliation1.中科院自动化研究所
2.中国科学院大学
First Author AffilicationInstitute of Automation, Chinese Academy of Sciences
Corresponding Author AffilicationInstitute of Automation, Chinese Academy of Sciences
Recommended Citation
GB/T 7714
Guo Peng,Ma Hong,Ruizhi Chen,et al. A High-Efficiency FPGA-Based Accelerator for Binarized Neural Network[J]. Journal of Circuits, Systems, and Computers,2019,28(1):1.
APA Guo Peng,Ma Hong,Ruizhi Chen,&Donglin Wang.(2019).A High-Efficiency FPGA-Based Accelerator for Binarized Neural Network.Journal of Circuits, Systems, and Computers,28(1),1.
MLA Guo Peng,et al."A High-Efficiency FPGA-Based Accelerator for Binarized Neural Network".Journal of Circuits, Systems, and Computers 28.1(2019):1.
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