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低密度奇偶校验（Low Density Parity Check，LDPC）码是Gallager在1962年提出的一种基于稀疏矩阵的线性分组码，具有逼近香农限的良好译码性能。随着相关研究的开展和计算机运算能力的发展，LDPC码已成为一种兼具性能优势和实用性的纠错码方案，被广泛地用于各种通信场景中，因此针对LDPC码的研究具有重要的理论价值和实用意义。

通用通信处理器（Universal Communication Processor，UCP）是中国科学院自动化研究所国家专用集成电路设计工程技术研究中心面向通信基站芯片海量数据、低延时、低功耗的需求，研发的一款完全自主知识产权的数字信号处理器，计算效率可与专用集成电路（Application Specific Integrated Circuit，ASIC）媲美，可灵活支撑通信领域各种核心算法。

本文针对第五代移动通信技术（5th Generation Mobile Communication Technology，5G）中的新空口（New Radio，NR）标准中的准循环（Quasi Cyclic，QC）LDPC码的编译码算法提出了算法创新和流程优化，降低了误码率和运算复杂度，且针对算法在UCP上的性能瓶颈定制了专用指令，提升了算法在UCP上的数据吞吐性能。基于以上工作提出了适用于UCP的高速并行编译码器的实现方案，该实现方案被UCP芯片设计所采纳，且进行了工程化流片验证。流片验证结果显示，本文提出的编译码器性能高于5G NR协议的性能要求，且与相关研究相比具有显著性能优势。论文的主要工作分为编码器和译码器两个方面。

编码器方面，针对QC-LDPC码快速迭代编码算法中长序列的循环移位，提出了一种字节并行可配置循环移位（Byte-Parallel Configurable Cyclic Shift，BP-CCS）算法。然后给出了BP-CCS算法在UCP上详细的硬件实现方案，其中针对拼接移位操作在UCP上的性能瓶颈，定制了专用的拼接移位（Splicing Shift）指令。最后基于BP-CCS算法模块构建了完整的LDPC编码器，并在UCP上进行了流片验证。流片验证结果表明，基于BP-CCS的LDPC编码器的数据吞吐性能远高于5G NR协议中约定性能，且具有灵活的可配置性。

译码器方面，针对最小和（Min-Sum，MS）算法引入的误差，提出了一种低复杂度修正最小和（Low-Complexity Corrected Min-Sum，LCC-MS）算法。然后给出了LCC-MS算法在UCP上详细的硬件实现方案，其中针对校验节点处理在UCP上的性能瓶颈，定制了专用的比较运算（CompMR）指令和绝对值比较选择（CompAbsSel）指令。最后基于LCC-MS算法构建了完整的LDPC译码器，并在UCP上进行了流片验证。流片验证结果表明，LCC-MS算法能够以较低的复杂度修正MS算法中引入的误差，在保证基于LCC-MS算法的LDPC译码器的数据吞吐性能显著高于5G NR协议中约定性能的同时降低了译码器的误码率。

Low Density Parity Check (LDPC) code is a linear block code based on sparse matrix proposed by Gallager in 1962, which has good decoding performance approaching the Shannon limit. With the development of related research and computer computing power, LDPC code has become an error correction code scheme with both performance advantages and practicability, and is widely used in various communication scenarios. Therefore, the research on LDPC code has important theoretical value and practical significance.

Universal Communication Processor (UCP) is a digital signal processor with completely independent intellectual property rights developed by the National Engineering \& Technology Research Center for Application Specific Integrated Circuit Design of the Institute of Automation, Chinese Academy of Sciences to meet the needs of communication base station chips for massive data, low latency and low power consumption. The computing efficiency of UCP is comparable to that of Application Specific Integrated Circuit (ASIC), which enables UCP to flexibly support various communication algorithms.

This paper proposes algorithm innovations and processe optimizations for the coding and decoding algorithms of Quasi Cyclic (QC) LDPC code in the New Radio (NR) standard in the 5th Generation Mobile Communication Technology (5G) standard, which reduces the bit error rate and computational complexity, and customizes special instructions for the performance bottleneck of the algorithm on UCP, which improves the data throughput performance of the algorithm on UCP. Based on the above work, an implementation scheme of high-speed parallel encoder and decoder suitable for UCP is proposed, which is adopted by UCP chip design and verified by engineering tape-out. The tape-out verification results show that the performance of the encoder and decoder proposed in this paper is higher than the performance requirements in the 5G NR protocol, and has significant performance advantages compared with related researches. The main work of the paper is divided into two aspects: encoder and decoder.

In terms of encoder, a Byte-Parallel Configurable Cyclic Shift (BP-CCS) algorithm is proposed for the cyclic shift of long sequences in the fast-iterative encoding algorithm of QC-LDPC code. Then, the detailed hardware implementation scheme of BP-CCS algorithm on UCP is given, in which a dedicated Splicing Shift instruction is customized for the performance bottleneck of splicing shift operation on UCP. Finally, a complete LDPC encoder is constructed based on the BP-CCS algorithm module, and the tape-out verification is performed on UCP. The tape-out verification results show that the data throughput performance of the LDPC encoder based on BP-CCS is much higher than the performance agreed in the 5G NR protocol, and the encoder has flexible configurability.

In terms of decoder, a Low-Complexity Corrected Min-Sum (LCC-MS) algorithm is proposed for the error introduced by the Min-Sum (MS) algorithm. Then, the detailed hardware implementation scheme of LCC-MS algorithm on UCP is given. In view of the performance bottleneck of check node processing on UCP, a dedicated comparison operation (CompMR) instruction and an absolute value comparison selection (CompAbsSel) instruction are customized. Finally, a complete LDPC decoder is constructed based on the LCC-MS algorithm, and the tape-out verification is performed on UCP. The tape-out verification results show that the LCC-MS algorithm can correct the errors introduced in the MS algorithm with low complexity, which can reduce the bit error rate of the decoder while ensuring that the data throughput performance of the decoder is much higher than the performance agreed in the 5G NR protocol.