CASIA OpenIR  > 毕业生  > 博士学位论文
集成电路后端设计优化关键技术研究
Alternative TitleResearch on Backend VLSI Design Optimization Techniques
路卢
Subtype工学博士
Thesis Advisor彭思龙
2009-07-02
Degree Grantor中国科学院研究生院
Place of Conferral中国科学院自动化研究所
Degree Discipline计算机应用技术
Keyword电路 版图 标准单元 互连线 结构化asic 特征化 逻辑效力 流程 优化 Circuit Layout Standard Cell Interconnect Structured Asic Characterize Logical Effort Flow Optimization
Abstract集成电路后端设计优化在集成电路设计过程中具有重要地位,包括一系列重要环节。本文针对集成电路后端设计优化中的问题,在如下几个方面开展了研究工作。 1. 针对结构化ASIC 单元设计问题,给出了一种具有良好可制造性、功能编程灵活性的细粒度的结构化ASIC 标准单元和互连线结构;给出了基于细粒度结构化ASIC 单元的步骤灵活的后端设计流程。 2. 针对单元性能参量特征化技术需求,给出了一个基于MC/DC 的高测试覆盖率的测试向量组生成方法;给出了全面揭示管脚种类、单元工作状态、可测参量等内容的相关性的关系矩阵;给出了一个基于开源脚本的易用的自动化标准单元性能特征化流程。 3. 将互连线负载引入现有逻辑效力方法,给出了一个简洁的扩展逻辑效力方法;基于经验证的仿真平台,给出了该方法公式的可靠的参数获取方法;以扩展逻辑效力方法为基础,结合路径延迟约束信息和版图设计约束,给出了一个计算效率高且易于工程使用的逻辑路径延迟优化方法。 理论和实验分析表明,上述各项技术在提升集成电路后端设计性能指标方面具有不同的作用,并在实践中取得了较好的效果。
Other AbstractBackend VLSI design plays an important role in VLSI design. In this thesis, several backend design techniques that may result good design outputs are proposed. 1. A group of fine-grained structured ASIC cells along with their metal interconnect structure, as well as modified backend design flow based on proposed structured ASIC solution are proposed aiming at better manufacture regularity, via programming ability and flow flexibility. 2. A MC/DC based method is proposed to help generating high coverage stimulus vectors. An open source script based fully automated characterizing flow is proposed upon thoroughly investigation of cell’s running conditions, measurable parameters and testing netlist files. 3. Extension on Logical Effort in awareness of interconnect delay is proposed along with a detail explanation of parameters calibrating method. The proposed Extended Logical Effort based path delay optimization flow can find both optimal gate sizes and interconnect wire segment lengths in high efficiency. Both analysis and experiments show that, techniques proposed here may bring various improvements on final design result.
shelfnumXWLW1457
Other Identifier200618014629093
Language中文
Document Type学位论文
Identifierhttp://ir.ia.ac.cn/handle/173211/6225
Collection毕业生_博士学位论文
Recommended Citation
GB/T 7714
路卢. 集成电路后端设计优化关键技术研究[D]. 中国科学院自动化研究所. 中国科学院研究生院,2009.
Files in This Item:
File Name/Size DocType Version Access License
CASIA_20061801462909(5339KB) 暂不开放CC BY-NC-SAApplication Full Text
Related Services
Recommend this item
Bookmark
Usage statistics
Export to Endnote
Google Scholar
Similar articles in Google Scholar
[路卢]'s Articles
Baidu academic
Similar articles in Baidu academic
[路卢]'s Articles
Bing Scholar
Similar articles in Bing Scholar
[路卢]'s Articles
Terms of Use
No data!
Social Bookmark/Share
All comments (0)
No comment.
 

Items in the repository are protected by copyright, with all rights reserved, unless otherwise indicated.