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基于SOI工艺抗辐照嵌入式SRAM关键技术研究
其他题名Research on Radiation Hardness-By-Design Embedded SRAM for ***nm Partially Depleted CMOS/SOI
刘丽
学位类型工学博士
导师李立健
2015-05-27
学位授予单位中国科学院大学
学位授予地点中国科学院自动化研究所
学位专业计算机应用技术
关键词绝缘体上硅 Kfz加固 单粒子翻转 静态随机存储器 Silcon-on-insulator(Soi) Radiation Hardness Sigle Event Upset(Seu) Static Random Access Memory(Sram)
摘要当电子器件应用在辐射环境下时,粒子流会与器件材料相互作用,使器件产生辐射损伤。该损伤导致器件电气特性发生改变,引起集成电路发生功能失效等不期望的工作状态。在军用、航天、核设施等关键应用系统中,需要FZ加固的电子器件。随着我国军事、航天事业快速发展,对FZ加固的大规模集成电路的需求急剧增加,其中高密度大容量的SRAM的KFZ加固是其中的重点和难点。研究KFZ加固的 SRAM 具有重要的现实意义和应用价值。 SOI技术用于FZ加固应用领域已有很多年,本论文基于国产**nm PD SOI工艺线,研究KFZSRAM的关键技术,完成频率达到**Hz SRAM电路设计。课题组首先初步研究SOI器件的辐射损伤机理,然后分析国产**nm PD SOI器件的性能,最终结合存储器的速度、面积、可靠性等指标,提出版图级、电路级等各层次FZ加固方案,完成高性能FZ加固SRAM电路设计。主要工作有: (1)分析国产**nm PD SOI器件的电气特性和KFZ性能。该工艺下的浮体器件存在历史效应、双极电流放大效应,不适宜用在存储器设计中。该工艺的体接触器件和同等特征尺寸的体硅器件相比,速度慢、功耗大、面积开销大。T型栅和H型栅体引出器件可增强器件抗单粒子能力,可以满足当前**rad(Si)的抗总剂量指标。 (2)提出两类抗单粒子翻转的存储单元,其读出速度快、面积开销较小,可用于实现低代价KFZSRAM存储体。这两类单元可同时适用于SOI以及体硅工艺。统计分析表明,使用该抗翻转存储单元可以达到KFZ加固软错误率指标。目前已对这两种电路结构申请专利。 (3)提出面向10T存储单元的可靠性评估方法。使用改进的SNM测试方法测量电压容限,使用直流分析的方式直观观测电流容限,可有效用于抗单粒子翻转存储单元的可靠性评估。 (4)通过理论推导和仿真试验分析锁存器型灵敏放大器的输出过程,指出预充电压、位线压差以及使能管和互锁反相器中下拉管的宽长比都是影响灵敏放大器速度的因素,提出初步的速度优化方案。然后阐明良率优化设计方法,即使用数值评估的方法对存储器读出系统的可靠性进行评估。通过良率敏感度分析可以为优化电路设计提供指导。 (5)完成了一款SRAM的电路设计。本存储器采用全定制设计,基于**nm PD SOI工艺实现,容量32kb。通过采用体引出器件、抗单粒子翻转的存储单元以及FZ加固电路设计技术实现存储器的FZ加固。
其他摘要It is observed that the radiation environment affects the performance and functionality of electronic devices due to ionizing particle’s interaction with device’s material. It is required that the electronic components have a certain level of radiation hardness in radiation environment especially for which is used in military, space and nuclear applications. With the rapid development of our country’s military and aerospace enterprises, the demand for radiation hardness large scale integrated circuit has increased dramatically, and radiation hardening technology for high density large capacity SRAM is a research emphasis. The research of radiation hardening SRAM has practical significance and application value. Silicon-on-insulator (SOI) technologies have been develop for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The research on radiation-hardened embedded SRAM for **nm partially depleted (PD) SOI is made in the dissertation. The damage mechanism of SOI CMOS MOSFETs in radiation environment is analyzed before evaluating the performance of **nm PD SOI MOSFETs. Finally, we make efforts to ensure the radiation hardness in layout design and schematic design and complete the circuit design. The main work consists in the following aspects: (1) The electrical responses and the radiation hardness characteristics of the **nm partially depleted SOI devices are examined. The floating body devices show history effect and bipolar currents, so cannot used in SRAM. The SOI devices that use body ties represent slower performance, occupy larger area and consume more power than the Si CMOS devices. The T-shape body ties and H-shape body ties improve SEE and TID tolerance. (2) To enhance SEU radiation protection, two SRAM memory cell are proposed. One consists of ten transistors with the area of **um2;The other consists of eight transistors with the area of **um2。They have a high speed, consume a relatively smaller area and are suitable for high density design with low cost. They can be used for not only SOI but also Si CMOS. These two schematic structures are applying for patent. (3)The evaluation method for 10T cell’s reliability is proposed. The voltage noise margin is measured with a modified SNM test; The current noise margin is get with a DC sweep analysis. (4) The delay of the sense amplifier (SA) is analyzed, and it shows that the pre-charge dc level, the input voltage difference and transist...
其他标识符201218014629094
语种中文
文献类型学位论文
条目标识符http://ir.ia.ac.cn/handle/173211/6712
专题毕业生_博士学位论文
推荐引用方式
GB/T 7714
刘丽. 基于SOI工艺抗辐照嵌入式SRAM关键技术研究[D]. 中国科学院自动化研究所. 中国科学院大学,2015.
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