It is observed that the radiation environment affects the performance and functionality of electronic devices due to ionizing particle’s interaction with device’s material. It is required that the electronic components have a certain level of radiation hardness in radiation environment especially for which is used in military, space and nuclear applications. With the rapid development of our country’s military and aerospace enterprises, the demand for radiation hardness large scale integrated circuit has increased dramatically, and radiation hardening technology for high density large capacity SRAM is a research emphasis. The research of radiation hardening SRAM has practical significance and application value. Silicon-on-insulator (SOI) technologies have been develop for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The research on radiation-hardened embedded SRAM for **nm partially depleted (PD) SOI is made in the dissertation. The damage mechanism of SOI CMOS MOSFETs in radiation environment is analyzed before evaluating the performance of **nm PD SOI MOSFETs. Finally, we make efforts to ensure the radiation hardness in layout design and schematic design and complete the circuit design. The main work consists in the following aspects： (1) The electrical responses and the radiation hardness characteristics of the **nm partially depleted SOI devices are examined. The floating body devices show history effect and bipolar currents, so cannot used in SRAM. The SOI devices that use body ties represent slower performance, occupy larger area and consume more power than the Si CMOS devices. The T-shape body ties and H-shape body ties improve SEE and TID tolerance. (2) To enhance SEU radiation protection, two SRAM memory cell are proposed. One consists of ten transistors with the area of **um2；The other consists of eight transistors with the area of **um2。They have a high speed, consume a relatively smaller area and are suitable for high density design with low cost. They can be used for not only SOI but also Si CMOS. These two schematic structures are applying for patent. (3)The evaluation method for 10T cell’s reliability is proposed. The voltage noise margin is measured with a modified SNM test; The current noise margin is get with a DC sweep analysis. (4) The delay of the sense amplifier (SA) is analyzed, and it shows that the pre-charge dc level, the input voltage difference and transist...
修改评论