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Alternative TitleA Study and Design of Parallel Multiplier with High Performance
Thesis Advisor王东琳
Degree Grantor中国科学院研究生院
Place of Conferral中国科学院自动化研究所
Degree Discipline模式识别与智能系统
Keyword乘法器 Booth算法 乘累加器 华莱氏树 Multiplier Booth Algorithm Mac Wallace Tree
Abstract高性能并行乘法器是现代数字信号处理器(DsP)的核心运算单元之一, 其完成一次乘法操作的时间决定了该DSP的工作频率。本文首先简单介绍了一 些常用的并行乘法器,然后详细研究了BOOTH乘法器。1300TH乘法器是采用BOOTH 算法设计的并行乘法器。现代高性能并行乘法器绝大多数都采用BOOTH算法, BOOTH算法可以将相加的部分积数量减少一半。利用BOOTH算法设计的并行乘法 器主要由三部分组成:BOOTH编码器,部分积迭加阵列和快速加法器。通过BOOTH 编码器产生的部分积是被乘数的5种倍数:O,±1,±2,针对不同的被乘数和 乘数的乘法本文推导了对应的BOOTH编码方法。部分积迭加阵列用来将这些部 分积迭加形成两个数:一个全部由进位组成,另一个全部由和组成。常用的部 分积迭加方法主要有华莱氏树,保留进位加法,压缩器等等。快速加法器用来 将两个数快速相加。本文介绍了几种常用的快速加法器:超前进位加法器(CLA), 进位选择加法器(CSI。A),条件和选择加法器(CSSA)等。 ZKLC乘法器是一个32位定浮点高性能并行乘法器,主要由五部分组成, 分别是指令码组合,乘数被乘数选择,BOOTH编码,部分积迭加和快速加法器。 ZKLC乘法器共有11条指令,包括定、浮点数乘法,定点数乘累加/减,对乘积 进行舍入及饱和操作等。本文对ZKLC乘法器的电路结构,指令意义以及指令的 执行过程均做了详细的介绍。 为了验证分析ZKLC乘法器的正确性,设计了一个32位定浮点乘法器,算 法采用ZKLC乘法器算法。设计的乘法器是混合描述方式,一部分直接给出网表, 另一部分采用行为级的描述方法。最后对设计的乘法器进行了验证。 设计的另一个10位定点补码乘累加器是用在一个2000阶的FIR滤波器中, 滤波器内部要求125个乘累加器并行使用。由于位数较少,因此设计时直接给 出网表,然后做逻辑仿真。设计采用BOOTH算法,类似于ZKLC乘法器,但做了 改进。经过在chartered.1 8工艺下的HSPICE仿真,完成一次乘累加时间小于 2ns,峰值电流为14mA左右。
Other AbstractFast parallel multiplier is an essential part of modem digital signal processor (DSP), and in many cases the system performance depends on the multiplication time. In this paper some commonly used multipliers are described firstly, and then BOOTH multiplier is studied in detail, including architecture and algorithm. BOOTH multiplier is implemented according to the BOOTH algorithm, which was first presented by A.D.Booth and is used by most modem parallel multipliers, since the partial products can be reduced to half in BOOTH multiplier. Three main parts compose BOOTH multiplier: BOOTH encoder, partial products adder and final fast adder. The multiplicand is transformed into partial products through BOOTH encoder by multiplying the multiplicand by 0, 4-1 or±2. We are clear about the BOOTH encoder algorithm for fixing point and float point through mathematical deduction, and it is the fundament of designing multiplier. Partial products adder is used to put together all the partial products to form two numbers: one is sums, the other is carryouts, these two numbers are combined to create the final product very fast through the fast adder. ZKLC multiplier is a 32-bit high performance parallel multiplier, which is composed of five parts: instruction codes combiner, multiplicand and multiplier selector, BOOTH encoder, partial products adder and final fast adder. The multiplier can perform 11 instructions, including fixing/float point multiplication, MAC, product rounding, saturation and so on. We propose a 32-bit multiplier to verify the algorithm of ZKLC multiplier. Another 10-bit 2's complement multiplier accumulator is designed, which is a part of a FIR filter. We make the netlist of the multiplier directly, since the multiplier is very simple and similar to ZKLC multiplier. Circuit simulation is performed in HSPICE(Chartered 0.18 μ m techinology)after logic verification. We find multiplication time is about 2ns, the peak current is 14mA, and so the multiplier can fulfill our requirement.
Other Identifier777
Document Type学位论文
Recommended Citation
GB/T 7714
刘建军. 高性能并行乘法器的研究与设计[D]. 中国科学院自动化研究所. 中国科学院研究生院,2004.
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