CASIA OpenIR  > 毕业生  > 硕士学位论文
Alternative TitleResearch and Design for Embeded SRAM with Dual Ports
Thesis Advisor王东琳
Degree Grantor中国科学院研究生院
Place of Conferral中国科学院自动化研究所
Degree Discipline模式识别与智能系统
Keyword嵌入式 存储器 Sram Embedded Memory Sram
Abstract高性能嵌入式存储器是现代数字信号处理器(DSP)的重要部件之一,特别随着 DSP芯片设计的 SOC 化,其容量的大小、工作频率的高低直接影响到系统对数据处理的速度和吞吐量。本文首先介绍了一些常见的嵌入式存储器,然后将其中在 DSP 芯片设计中最常见的两种嵌入式存储器 SRAM 和 DRAM 相互比较,并详尽的研究了 SRAM 存储器。SRAM存储器采用的是 SRAM 存储单元,具有读写速度快、可制造性高等优点,其电路结构通常分为存储矩阵、地址译码器和读/写控制电路三部分。ZKLC-0201 是一种高性能的 32 位数字信号处理器(DSP),内部有双端口 SRAM 和 I/0 外设,这些外设受专门的 I/O 总线支持,从而形成了一个完整的片上系统。利用片内的指令缓冲,处理器执行指令的时间可以是一个单周期。ZKLC-0201 结合了一个性能优良的浮点DSP 核以及丰富的片上功能,这些功能有主机接口、DMA 控制器、串口、链路口以及可用于多处理机系统的总线连接方式。ZKLC-0201 的超级哈佛结构:一个纵横式的总线(CrossbarBus)交换机将一个数字处理器(Numeric Processor)核与一个独立的 I/O 处理器(I/0Processor)、双口(Dual-Potted)存储器(Memory)、并行的系统总线(Parallel System Bus)等连接起来。ZKLC-0201中的双端口嵌入式存储器是一个应用于高性能DSP处理器中的 SRAM 存储器,支持对 16 比特、32 比特、40 比特和 48 比特 4 种不同长度数据的存取。本文首先从系统设计、体系结构和其所需要达到的性能指标进行分析上对双端口嵌入式存储器进行分析;然后,从电路结构上将其分为存储阵列、读写电路、数据通路及其控制电路、地址译码和冗余控制五部分,并逐一进行分析和设计,并对双端口实现、接口设计、时序设计、电路结构设计、存储器测试设计均作了详细的介绍。 嵌入式存储器 IP 软核设计的主要作用在于验证系统设计,并为工程中心下一步的设计仿真工作进行准备,设计上采用混合设计的描述方法,并对设计的存储器 IP 软核进行了验证。
Other AbstractEmbedded SRAM memory with high performances is an important part of the current digital signal processor (DSP). As the design of DSP chip adopts SOC technology especially, the capacity or main frequency of an embedded memory has a direct influence on the data processing velocity and access of the system. This paper describes some of popular embedded memory first. Then the comparing the embedded SRAM with the embedded DRAM, which are widely included in DSP chip, is done. Finally an exhaustive study of the SRAM is made. SRAM consists of SRAM storage elements. Its reading or writing speed is fast. It is manufactured easier also. The circuit architecture of SRAM includes storage matrix, address decoder and controller of access. ZKLC-0201 is a high performance 32-bits DSP. Inside it there is dual ports SRAM and I/O peripheral that is supported by the special bus. In this way, it is a completed system on chip. ZKLC-0201 consists of excellent float DSP core and rich functions on chip. They are main interfaces, DMA controller, series ports, chain ports and connective way for multi-processors. ZKLC-0201 super Harvard structure makes a crossbar bus, a numeric processor, a single I/O, dual-potted memory, parallel system bus be connected together. ZKLC-0201 embedded memory with dual ports is the memory that is applied in the high performance DSP. It can access four kinds of data, the length of which are 16-bits, 32-bits, 40-bis and 48-bits.In this paper, the analysis on the embedded memory with dual ports is made based upon the system design, the architecture structure, the achieved performances and features. Secondly, the memory is decomposed into storage array, read-write circuit, data channel end control circuit, address decoder and redundancy control. Finally each part of the memory is analyzed and designed. The description about dual ports realization, interface design, time sequencing design, circuit structure design and memory testing design is presented in detail.The IP soft-core design for embedded memory plays an important part in testing system design, and makes preparation for system imitation in advance. A mixed design method is applied, and the testing on the IP soft core of the designed memory is achieved.
Other Identifier200228014603539
Document Type学位论文
Recommended Citation
GB/T 7714
成嵩. 高性能双端口嵌入式存储器的研究与设计[D]. 中国科学院自动化研究所. 中国科学院研究生院,2005.
Files in This Item:
There are no files associated with this item.
Related Services
Recommend this item
Usage statistics
Export to Endnote
Google Scholar
Similar articles in Google Scholar
[成嵩]'s Articles
Baidu academic
Similar articles in Baidu academic
[成嵩]'s Articles
Bing Scholar
Similar articles in Bing Scholar
[成嵩]'s Articles
Terms of Use
No data!
Social Bookmark/Share
All comments (0)
No comment.

Items in the repository are protected by copyright, with all rights reserved, unless otherwise indicated.