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| A 5G-Oriented LDPC Encoder Based on Byte-Parallel Configurable Cyclic Shift 会议论文 , Chongqing, China, 2021-6-5 作者: Sun, Yisong; Li, Huan; Guo, Chen; Wang, Donglin Adobe PDF(9208Kb)  |  收藏  |  浏览/下载:179/35  |  提交时间:2022/06/14 5G LDPC encoder BP-CCS UCP |
| A High-Efficiency FPGA-Based Accelerator for Binarized Neural Network 期刊论文 Journal of Circuits, Systems, and Computers, 2019, 卷号: 28, 期号: 1, 页码: 1 作者: Guo Peng; Ma Hong; Ruizhi Chen; Donglin Wang 浏览  |  Adobe PDF(1487Kb)  |  收藏  |  浏览/下载:305/134  |  提交时间:2019/06/17 Cnn Bnn Fpga Accelerator |
| A Bypass-Based Low Latency Network-on-Chip Router 期刊论文 IEICE Electronics Express, 2019, 卷号: 16, 期号: 4, 页码: 1 作者: Guo Peng; Qingbin Liu; Ruizhi Chen; Lei Yang; Donglin Wang 浏览  |  Adobe PDF(1881Kb)  |  收藏  |  浏览/下载:272/92  |  提交时间:2019/06/17 Network-on-chip Router Bypass Low Latency |
| A Design Space Exploration Method for on-Chip Memory System Based on Task Scheduling 会议论文 , Beijing,China, 2018,11.23-25 作者: Hongyu,Meng; Pengfei.Ding; Mingxuan.Wang; Donglin.Wang 浏览  |  Adobe PDF(288Kb)  |  收藏  |  浏览/下载:281/100  |  提交时间:2019/05/06 Design Space Exploration Multi-core Architecture Memory System Task Scheduling |
| Parallel Polar Encoding in 5G Communication 会议论文 , 巴西纳塔尔, 2018-6 作者: Yang Guo; Shaolin Xie; Zijun Liu; Lei Yang; Donglin Wang 浏览  |  Adobe PDF(377Kb)  |  收藏  |  浏览/下载:329/112  |  提交时间:2019/05/10 |
| FBNA: A Fully Binarized Neural Network Accelerator 会议论文 , 爱尔兰都柏林, 2018-8 作者: Guo Peng; Hong Ma; Ruizhi Chen; Pin Li; Shaolin Xie; Donglin Wang 浏览  |  Adobe PDF(824Kb)  |  收藏  |  浏览/下载:366/139  |  提交时间:2019/06/17 |
| A Low-Complexity Min-Sum Decoding Algorithm for LDPC Codes 会议论文 , 中国四川, 2017.10.27-2017.10.30 作者: Li H; Guo J; Guo C; Wang D 浏览  |  Adobe PDF(285Kb)  |  收藏  |  浏览/下载:465/205  |  提交时间:2018/06/01 Ldpc Decoding Low-complexity Min-sum Simplified Check Nodes |
| A High-Parallelism Detection Algorithm for Massive MIMO Systems 会议论文 , 中国深圳, 2017.07.23-2017.07.26 作者: Li H; Zhao X; Guo C; Wang D 浏览  |  Adobe PDF(303Kb)  |  收藏  |  浏览/下载:256/60  |  提交时间:2018/06/01 Massive Mimo Signal Detection High Parallelism Matrix Blocking |
| MaPU: A Novel Mathematical Computing Architecture 会议论文 http://hpca22.site.ac.upc.edu, Barcelona, Spain, March 12-16 2016 作者: Donglin Wang; Shaolin Xie; Zhiwei Zhang; Xueliang Du; Lei Wang; Zijun Liu; shaolin.xie@ia.ac.cn 浏览  |  Adobe PDF(2051Kb)  |  收藏  |  浏览/下载:721/183  |  提交时间:2016/04/07 Computer Architecture Vlsi High Performance Computing |
| Parallel Implementation of Arbitrary-Sized Discrete Fourier Transform on FPGA 会议论文 2016 3rd International Conference on Advanced Computing and Communication Systems (ICACCS -2016), Coimbatore, INDIA, 2016.01.22-2016.01.23 作者: Shu Lin; Hao,Jie; Li,Chengcheng; Feng,Hui; Wang,Donglin; Shu,Lin 浏览  |  Adobe PDF(368Kb)  |  收藏  |  浏览/下载:344/85  |  提交时间:2016/06/27 Dft Arbitrary-sized Parallel Fpga |