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| A 5G-Oriented LDPC Encoder Based on Byte-Parallel Configurable Cyclic Shift 会议论文 , Chongqing, China, 2021-6-5 作者: Sun, Yisong; Li, Huan; Guo, Chen; Wang, Donglin Adobe PDF(9208Kb)  |  收藏  |  浏览/下载:181/35  |  提交时间:2022/06/14 5G LDPC encoder BP-CCS UCP |
| A reconfigurable computing architecture for 5G communication 期刊论文 Journal of Central South University, 2019, 期号: 0, 页码: 0 作者: GUO Yang; LIU Zi-Jun; YANG Lei; LI Huan; WANG Dong-Lin 浏览  |  Adobe PDF(913Kb)  |  收藏  |  浏览/下载:433/129  |  提交时间:2019/07/11 5g Instruction Set Register File Code Compression Throughput Power Consumption. |
| 卷积神经网络高效计算关键技术研究 学位论文 , 中国科学院自动化研究所: 中国科学院大学, 2019 作者: 郭鹏 Adobe PDF(5436Kb)  |  收藏  |  浏览/下载:273/11  |  提交时间:2019/06/17 深度神经网络 卷积神经网络 二值网络 低比特量化 神经网络加速器 |
| A Design Space Exploration Method for on-Chip Memory System Based on Task Scheduling 会议论文 , Beijing,China, 2018,11.23-25 作者: Hongyu,Meng; Pengfei.Ding; Mingxuan.Wang; Donglin.Wang Adobe PDF(288Kb)  |  收藏  |  浏览/下载:281/100  |  提交时间:2019/05/06 Design Space Exploration Multi-core Architecture Memory System Task Scheduling |
| Accelerate Convolutional Neural Network with a customized VLIW DSP 会议论文 , 北京, 2018-10 作者: Guo Peng; Ma Hong; Guo Ruoshan; Liu Zhuang; Li Pin; Wang Donglin 浏览  |  Adobe PDF(1173Kb)  |  收藏  |  浏览/下载:319/121  |  提交时间:2019/06/17 |
| Parallel Polar Encoding in 5G Communication 会议论文 , 巴西纳塔尔, 2018-6 作者: Yang Guo; Shaolin Xie; Zijun Liu; Lei Yang; Donglin Wang 浏览  |  Adobe PDF(377Kb)  |  收藏  |  浏览/下载:330/113  |  提交时间:2019/05/10 |
| A reconfigurable high-performance multiplier based on multi-granularity design and parallel acceleration 会议论文 , 中国科技会堂, 2017-11 作者: Feng Jing; Zijun Liu; Xiaojun Ma; Guo Yang; Guo Peng; Donglin Wang 浏览  |  Adobe PDF(576Kb)  |  收藏  |  浏览/下载:496/195  |  提交时间:2018/05/31 Compression High Speed Multi-granularity Parallel Power Efficient Reuse Reconfigurable |
| A Self-Indexed Register File for Efficient Arithmetical Computing Hardware 会议论文 , UK, 2017-10 作者: Lei Yang; Shaolin Xie; Zijun Liu; Xueliang Du; DongLin Wang 浏览  |  Adobe PDF(707Kb)  |  收藏  |  浏览/下载:301/70  |  提交时间:2018/05/07 Register File Arithmetical Computing Energy Efficient |
| A reconfigurable ASIC-like image polyphase interpolation implementation method 会议论文 , ShenZhen, 2017-7 作者: Lei Yang; Ruoshan Guo; Shaolin Xie; Donglin Wang 浏览  |  Adobe PDF(210Kb)  |  收藏  |  浏览/下载:327/110  |  提交时间:2018/05/07 Image Interpolation Acceleration Reconfigurable Implementation |
| A High Performance Multi-standard Viterbi Decoder 会议论文 , Shenzhen, China, July 21-23, 2017 作者: Zhao, Xuying; Li, Huan; Wang, Xiaoqin 浏览  |  Adobe PDF(340Kb)  |  收藏  |  浏览/下载:325/105  |  提交时间:2017/12/07 Viterbi Decoder Multi-standard High Performance Forward Traceback Sliding Window |