已选(0)清除
条数/页: 排序方式: |
| A reconfigurable computing architecture for 5G communication 期刊论文 Journal of Central South University, 2019, 期号: 0, 页码: 0 作者: GUO Yang; LIU Zi-Jun; YANG Lei; LI Huan; WANG Dong-Lin Adobe PDF(913Kb)  |  收藏  |  浏览/下载:398/127  |  提交时间:2019/07/11 5g Instruction Set Register File Code Compression Throughput Power Consumption. |
| A Distributed Register File Architecture Based on Dynamic Scheduling for VLIW Machine 会议论文 , 北京, 2018-6 作者: Yang Guo; Donglin Wang; Zijun Liu; Hongyu Meng Adobe PDF(203Kb)  |  收藏  |  浏览/下载:283/116  |  提交时间:2019/05/10 |
| A reconfigurable high-performance multiplier based on multi-granularity design and parallel acceleration 会议论文 , 中国科技会堂, 2017-11 作者: Feng Jing; Zijun Liu; Xiaojun Ma; Guo Yang; Guo Peng; Donglin Wang Adobe PDF(576Kb)  |  收藏  |  浏览/下载:466/194  |  提交时间:2018/05/31 Compression High Speed Multi-granularity Parallel Power Efficient Reuse Reconfigurable |
| A Self-Indexed Register File for Efficient Arithmetical Computing Hardware 会议论文 , UK, 2017-10 作者: Lei Yang; Shaolin Xie; Zijun Liu; Xueliang Du; DongLin Wang Adobe PDF(707Kb)  |  收藏  |  浏览/下载:295/69  |  提交时间:2018/05/07 Register File Arithmetical Computing Energy Efficient |
| MaPU: A Novel Mathematical Computing Architecture 会议论文 http://hpca22.site.ac.upc.edu, Barcelona, Spain, March 12-16 2016 作者: Donglin Wang; Shaolin Xie; Zhiwei Zhang; Xueliang Du; Lei Wang; Zijun Liu; shaolin.xie@ia.ac.cn Adobe PDF(2051Kb)  |  收藏  |  浏览/下载:671/180  |  提交时间:2016/04/07 Computer Architecture Vlsi High Performance Computing |