CASIA OpenIR

浏览/检索结果: 共3条,第1-3条 帮助

限定条件    
已选(0)清除 条数/页:   排序方式:
Traffic-Aware and Memory-Aware Task Scheduling on Multi-Core Chips 会议论文
, Beijing,China, 2018,11.23-25
作者:  Hongyu,Meng;  Yang,Guo;  Zijun.Liu;  Donglin.Wang
浏览  |  Adobe PDF(345Kb)  |  收藏  |  浏览/下载:283/96  |  提交时间:2019/05/06
Task Scheduling  Multi-core  Shared Memory  Traffic-aware  Memory-aware  
A Design Space Exploration Method for on-Chip Memory System Based on Task Scheduling 会议论文
, Beijing,China, 2018,11.23-25
作者:  Hongyu,Meng;  Pengfei.Ding;  Mingxuan.Wang;  Donglin.Wang
浏览  |  Adobe PDF(288Kb)  |  收藏  |  浏览/下载:279/100  |  提交时间:2019/05/06
Design Space Exploration  Multi-core Architecture  Memory System  Task Scheduling  
A high-throughput network on-chip in full-mesh architecture 期刊论文
IEICE ELEX, 2018, 卷号: 15, 期号: 17, 页码: 1-12
作者:  Hongyu,Meng;  Lei,Yang;  Zijun.Liu;  Donglin.Wang
浏览  |  Adobe PDF(2525Kb)  |  收藏  |  浏览/下载:277/102  |  提交时间:2019/05/06
Network On-chip  Full-mesh  High Connectivity  Multi-core