CASIA OpenIR

Browse/Search Results:  1-4 of 4 Help

Filters    
Selected(0)Clear Items/Page:    Sort:
A Distributed Register File Architecture Based on Dynamic Scheduling for VLIW Machine 会议论文
, 北京, 2018-6
Authors:  Yang Guo;  Donglin Wang;  Zijun Liu;  Hongyu Meng
View  |  Adobe PDF(203Kb)  |  Favorite  |  View/Download:339/133  |  Submit date:2019/05/10
A Design Space Exploration Method for on-Chip Memory System Based on Task Scheduling 会议论文
, Beijing,China, 2018,11.23-25
Authors:  Hongyu,Meng;  Pengfei.Ding;  Mingxuan.Wang;  Donglin.Wang
View  |  Adobe PDF(288Kb)  |  Favorite  |  View/Download:312/109  |  Submit date:2019/05/06
Design Space Exploration  Multi-core Architecture  Memory System  Task Scheduling  
Traffic-Aware and Memory-Aware Task Scheduling on Multi-Core Chips 会议论文
, Beijing,China, 2018,11.23-25
Authors:  Hongyu,Meng;  Yang,Guo;  Zijun.Liu;  Donglin.Wang
View  |  Adobe PDF(345Kb)  |  Favorite  |  View/Download:325/105  |  Submit date:2019/05/06
Task Scheduling  Multi-core  Shared Memory  Traffic-aware  Memory-aware  
Advanced Extensible Crossbar Protocol for Connecting Multi-Cores and Shared-Memory on Chip 会议论文
, Beijing,China, 2018,6.15-17
Authors:  Hongyu,Meng;  Donglin,Wang;  Zijun,Liu;  Yang,Guo
View  |  Adobe PDF(318Kb)  |  Favorite  |  View/Download:344/118  |  Submit date:2019/05/06
Interconnect  Crossbar  Multi-cores  Shared-memory