CASIA OpenIR
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A Distributed Register File Architecture Based on Dynamic Scheduling for VLIW Machine 会议论文
, 北京, 2018-6
Authors:  Yang Guo;  Donglin Wang;  Zijun Liu;  Hongyu Meng
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A Design Space Exploration Method for on-Chip Memory System Based on Task Scheduling 会议论文
, Beijing,China, 2018,11.23-25
Authors:  Hongyu,Meng;  Pengfei.Ding;  Mingxuan.Wang;  Donglin.Wang
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Design Space Exploration  Multi-core Architecture  Memory System  Task Scheduling  
Traffic-Aware and Memory-Aware Task Scheduling on Multi-Core Chips 会议论文
, Beijing,China, 2018,11.23-25
Authors:  Hongyu,Meng;  Yang,Guo;  Zijun.Liu;  Donglin.Wang
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Task Scheduling  Multi-core  Shared Memory  Traffic-aware  Memory-aware  
A high-throughput network on-chip in full-mesh architecture 期刊论文
IEICE ELEX, 2018, 卷号: 15, 期号: 17, 页码: 1-12
Authors:  Hongyu,Meng;  Lei,Yang;  Zijun.Liu;  Donglin.Wang
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Network On-chip  Full-mesh  High Connectivity  Multi-core  
Advanced Extensible Crossbar Protocol for Connecting Multi-Cores and Shared-Memory on Chip 会议论文
, Beijing,China, 2018,6.15-17
Authors:  Hongyu,Meng;  Donglin,Wang;  Zijun,Liu;  Yang,Guo
View  |  Adobe PDF(318Kb)  |  Favorite  |  View/Download:344/118  |  Submit date:2019/05/06
Interconnect  Crossbar  Multi-cores  Shared-memory