中文版 | English

在结果中检索

CASIA OpenIR

浏览/检索结果: 共5条，第1-5条 帮助

限定条件    
已选(0)清除 条数/页：   排序方式：
An approach to build cycle accurate full system VLIW simulation platform 期刊论文
SIMULATION MODELLING PRACTICE AND THEORY, 2016, 卷号: 67, 期号: 2016, 页码: 14-28
作者:  Yang, Lei;  Wang, Lei;  Zhang, Xing;  Wang, DongLin
浏览  |  Adobe PDF(2567Kb)  |  收藏  |  浏览/下载：371/130  |  提交时间：2016/12/26
Vliw Simulation  Cycle Accurate  Heterogeneous Computing  
Optimal Many-to-Many Personalized Concurrent Communication in RapidIO-based Fat-trees 会议论文
17th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing (SNPD 2016), Shanghai,China, 2016.05.30-2016.06.01
作者:  Shu Lin;  Hao,Jie;  Song,Yafang;  Li,Chengcheng;  Wang,Donglin;  Shu,Lin
Adobe PDF(775Kb)  |  收藏  |  浏览/下载：336/57  |  提交时间：2016/06/27
Many-to-many  Personalized  Rapidio  Fat-tree  Node-level  Congestion-avoidance  
Collection of charge in NMOS from single event effect 期刊论文
IEICE ELECTRONICS EXPRESS, 2016, 卷号: 13, 期号: 8, 页码: 1-8
作者:  Wang, Jingqiu;  Lin, Fujiang;  Wang, Donglin;  Song, Wenna;  Liu, Li;  Song, Qiwei;  Chen, Liang
Adobe PDF(2518Kb)  |  收藏  |  浏览/下载：275/59  |  提交时间：2016/09/30
Single Event Effect  Ultra Deep Sub-micron  Double Exponential Transient Current Model  Multi-dimensional  
MaPU: A Novel Mathematical Computing Architecture 会议论文
http://hpca22.site.ac.upc.edu, Barcelona, Spain, March 12-16 2016
作者:  Donglin Wang;  Shaolin Xie;  Zhiwei Zhang;  Xueliang Du;  Lei Wang;  Zijun Liu;  shaolin.xie@ia.ac.cn
浏览  |  Adobe PDF(2051Kb)  |  收藏  |  浏览/下载：699/182  |  提交时间：2016/04/07
Computer Architecture  Vlsi  High Performance Computing  
Parallel Implementation of Arbitrary-Sized Discrete Fourier Transform on FPGA 会议论文
2016 3rd International Conference on Advanced Computing and Communication Systems (ICACCS -2016), Coimbatore, INDIA, 2016.01.22-2016.01.23
作者:  Shu Lin;  Hao,Jie;  Li,Chengcheng;  Feng,Hui;  Wang,Donglin;  Shu,Lin
Adobe PDF(368Kb)  |  收藏  |  浏览/下载：341/85  |  提交时间：2016/06/27
Dft  Arbitrary-sized  Parallel  Fpga