CASIA OpenIR

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A bypass-based low latency network-on-chip router 期刊论文
IEICE ELECTRONICS EXPRESS, 2019, 卷号: 16, 期号: 4, 页码: 12
Authors:  Guo, Peng;  Liu, Qingbin;  Chen, Ruizhi;  Yang, Lei;  Wang, Donglin
Favorite  |  View/Download:5/0  |  Submit date:2019/04/23
network-on-chip  router  bypass  low latency  
Parallel Polar Encoding in 5G Communication 会议论文
, 巴西纳塔尔, 2018-6
Authors:  Yang Guo;  Shaolin Xie;  Zijun Liu;  Lei Yang;  Donglin Wang
View  |  Adobe PDF(377Kb)  |  Favorite  |  View/Download:25/3  |  Submit date:2019/05/10
Advanced Extensible Crossbar Protocol for Connecting Multi-Cores and Shared-Memory on Chip 会议论文
, Beijing,China, 2018,6.15-17
Authors:  Hongyu,Meng;  Donglin,Wang;  Zijun,Liu;  Yang,Guo
View  |  Adobe PDF(318Kb)  |  Favorite  |  View/Download:12/1  |  Submit date:2019/05/06
Interconnect  Crossbar  Multi-cores  Shared-memory  
A Distributed Register File Architecture Based on Dynamic Scheduling for VLIW Machine 会议论文
, 北京, 2018-6
Authors:  Yang Guo;  Donglin Wang;  Zijun Liu;  Hongyu Meng
View  |  Adobe PDF(203Kb)  |  Favorite  |  View/Download:22/3  |  Submit date:2019/05/10
Progress in a novel architecture for high performance processing 期刊论文
JAPANESE JOURNAL OF APPLIED PHYSICS, 2018, 卷号: 57, 期号: 4
Authors:  Zhang, Zhiwei;  Liu, Meng;  Liu, Zijun;  Du, Xueliang;  Xie, Shaolin;  Ma, Hong;  Ding, Guangxin;  Ren, Weili;  Zhou, Fabiao;  Sun, Wenqin;  Wang, Huijuan;  Wang, Donglin
Favorite  |  View/Download:41/0  |  Submit date:2018/10/10
A reconfigurable high-performance multiplier based on multi-granularity design and parallel acceleration 会议论文
, 中国科技会堂, 2017-11
Authors:  Feng Jing;  Zijun Liu;  Xiaojun Ma;  Guo Yang;  Guo Peng;  Donglin Wang
View  |  Adobe PDF(576Kb)  |  Favorite  |  View/Download:94/22  |  Submit date:2018/05/31
Compression  High Speed  Multi-granularity  Parallel  Power Efficient  Reuse  Reconfigurable  
基于滑窗流水的高性能可配置viterbi译码器 期刊论文
微电子学与计算机, 2018, 卷号: 35, 期号: 2, 页码: 32-36
Authors:  赵旭莹;  李桓;  王晓琴;  王东琳
View  |  Adobe PDF(405Kb)  |  Favorite  |  View/Download:87/11  |  Submit date:2018/04/24
可配置  Viterbi译码器  高性能  滑窗流水  前向回溯  
A Self-Indexed Register File for Efficient Arithmetical Computing Hardware 会议论文
, UK, 2017-10
Authors:  Lei Yang;  Shaolin Xie;  Zijun Liu;  Xueliang Du;  DongLin Wang
View  |  Adobe PDF(707Kb)  |  Favorite  |  View/Download:76/13  |  Submit date:2018/05/07
Register File  Arithmetical Computing  Energy Efficient  
A reconfigurable ASIC-like image polyphase interpolation implementation method 会议论文
, ShenZhen, 2017-7
Authors:  Lei Yang;  Ruoshan Guo;  Shaolin Xie;  Donglin Wang
View  |  Adobe PDF(210Kb)  |  Favorite  |  View/Download:63/10  |  Submit date:2018/05/07
Image Interpolation  Acceleration  Reconfigurable Implementation  
A novel obstacle-aware multiple fan-out symmetrical clock tree synthesis 期刊论文
IEICE ELECTRONICS EXPRESS, 2017, 卷号: 14, 期号: 20
Authors:  Liu, Meng;  Zhang, Zhiwei;  Sun, Wenqin;  Wang, Donglin
Favorite  |  View/Download:33/0  |  Submit date:2018/10/10
Symmetrical Clock Tree  Multiple Fan-out  Matching Algorithm  Buffer Insertion  Obstacle-aware Placement And Routing