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A reconfigurable computing architecture for 5G communication 期刊论文
Journal of Central South University, 2019, 期号: 0, 页码: 0
Authors:  GUO Yang;  LIU Zi-Jun;  YANG Lei;  LI Huan;  WANG Dong-Lin
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5g  Instruction Set  Register File  Code Compression  Throughput  Power Consumption.  
A High-Efficiency FPGA-Based Accelerator for Binarized Neural Network 期刊论文
Journal of Circuits, Systems, and Computers, 2019, 卷号: 28, 期号: 1, 页码: 1
Authors:  Guo Peng;  Ma Hong;  Ruizhi Chen;  Donglin Wang
View  |  Adobe PDF(1487Kb)  |  Favorite  |  View/Download:63/40  |  Submit date:2019/06/17
Cnn  Bnn  Fpga  Accelerator  
A bypass-based low latency network-on-chip router 期刊论文
IEICE ELECTRONICS EXPRESS, 2019, 卷号: 16, 期号: 4, 页码: 12
Authors:  Guo, Peng;  Liu, Qingbin;  Chen, Ruizhi;  Yang, Lei;  Wang, Donglin
Favorite  |  View/Download:30/0  |  Submit date:2019/04/23
network-on-chip  router  bypass  low latency  
A Bypass-Based Low Latency Network-on-Chip Router 期刊论文
IEICE Electronics Express, 2019, 卷号: 16, 期号: 4, 页码: 1
Authors:  Guo Peng;  Qingbin Liu;  Ruizhi Chen;  Lei Yang;  Donglin Wang
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Network-on-chip  Router  Bypass  Low Latency  
Fast and Efficient Deep Sparse Multi-Strength Spiking Neural Networks with Dynamic Pruning 会议论文
, 巴西里约热内卢, 2018-7
Authors:  Chen RZ(陈睿智);  Ma H(马鸿);  Xie SL(谢少林);  Guo P(郭鹏);  Li P(李品);  Wang DL(王东琳)
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Low Latency Spiking ConvNets with Restricted Output Training and False Spike Inhibition 会议论文
, 巴西里约热内卢, 2018-7
Authors:  Chen RZ(陈睿智);  Ma H(马鸿);  Guo P(郭鹏);  Xie SL(谢少林);  Wang DL(王东琳)
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Accelerate Convolutional Neural Network with a customized VLIW DSP 会议论文
, 北京, 2018-10
Authors:  Guo Peng;  Ma Hong;  Guo Ruoshan;  Liu Zhuang;  Li Pin;  Wang Donglin
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Parallel Polar Encoding in 5G Communication 会议论文
, 巴西纳塔尔, 2018-6
Authors:  Yang Guo;  Shaolin Xie;  Zijun Liu;  Lei Yang;  Donglin Wang
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Advanced Extensible Crossbar Protocol for Connecting Multi-Cores and Shared-Memory on Chip 会议论文
, Beijing,China, 2018,6.15-17
Authors:  Hongyu,Meng;  Donglin,Wang;  Zijun,Liu;  Yang,Guo
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Interconnect  Crossbar  Multi-cores  Shared-memory  
A Distributed Register File Architecture Based on Dynamic Scheduling for VLIW Machine 会议论文
, 北京, 2018-6
Authors:  Yang Guo;  Donglin Wang;  Zijun Liu;  Hongyu Meng
View  |  Adobe PDF(203Kb)  |  Favorite  |  View/Download:44/9  |  Submit date:2019/05/10