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A reconfigurable computing architecture for 5G communication 期刊论文
Journal of Central South University, 2019, 期号: 0, 页码: 0
Authors:  GUO Yang;  LIU Zi-Jun;  YANG Lei;  LI Huan;  WANG Dong-Lin
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5g  Instruction Set  Register File  Code Compression  Throughput  Power Consumption.  
Traffic-Aware and Memory-Aware Task Scheduling on Multi-Core Chips 会议论文
, Beijing,China, 2018,11.23-25
Authors:  Hongyu,Meng;  Yang,Guo;  Zijun.Liu;  Donglin.Wang
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Task Scheduling  Multi-core  Shared Memory  Traffic-aware  Memory-aware  
A high-throughput network on-chip in full-mesh architecture 期刊论文
IEICE ELEX, 2018, 卷号: 15, 期号: 17, 页码: 1-12
Authors:  Hongyu,Meng;  Lei,Yang;  Zijun.Liu;  Donglin.Wang
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Network On-chip  Full-mesh  High Connectivity  Multi-core  
Parallel Polar Encoding in 5G Communication 会议论文
, 巴西纳塔尔, 2018-6
Authors:  Yang Guo;  Shaolin Xie;  Zijun Liu;  Lei Yang;  Donglin Wang
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A Distributed Register File Architecture Based on Dynamic Scheduling for VLIW Machine 会议论文
, 北京, 2018-6
Authors:  Yang Guo;  Donglin Wang;  Zijun Liu;  Hongyu Meng
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Advanced Extensible Crossbar Protocol for Connecting Multi-Cores and Shared-Memory on Chip 会议论文
, Beijing,China, 2018,6.15-17
Authors:  Hongyu,Meng;  Donglin,Wang;  Zijun,Liu;  Yang,Guo
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Interconnect  Crossbar  Multi-cores  Shared-memory  
Progress in a novel architecture for high performance processing 期刊论文
JAPANESE JOURNAL OF APPLIED PHYSICS, 2018, 卷号: 57, 期号: 4
Authors:  Zhang, Zhiwei;  Liu, Meng;  Liu, Zijun;  Du, Xueliang;  Xie, Shaolin;  Ma, Hong;  Ding, Guangxin;  Ren, Weili;  Zhou, Fabiao;  Sun, Wenqin;  Wang, Huijuan;  Wang, Donglin
Favorite  |  View/Download:55/0  |  Submit date:2018/10/10
A reconfigurable high-performance multiplier based on multi-granularity design and parallel acceleration 会议论文
, 中国科技会堂, 2017-11
Authors:  Feng Jing;  Zijun Liu;  Xiaojun Ma;  Guo Yang;  Guo Peng;  Donglin Wang
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Compression  High Speed  Multi-granularity  Parallel  Power Efficient  Reuse  Reconfigurable  
A Self-Indexed Register File for Efficient Arithmetical Computing Hardware 会议论文
, UK, 2017-10
Authors:  Lei Yang;  Shaolin Xie;  Zijun Liu;  Xueliang Du;  DongLin Wang
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Register File  Arithmetical Computing  Energy Efficient  
MaPU: A Novel Mathematical Computing Architecture 会议论文
http://hpca22.site.ac.upc.edu, Barcelona, Spain, March 12-16 2016
Authors:  Donglin Wang;  Shaolin Xie;  Zhiwei Zhang;  Xueliang Du;  Lei Wang;  Zijun Liu;  shaolin.xie@ia.ac.cn
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Computer Architecture  Vlsi  High Performance Computing