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A high-throughput network on-chip in full-mesh architecture
Hongyu,Meng1,2; Lei,Yang1; Zijun.Liu1; Donglin.Wang1
Source PublicationIEICE ELEX

Just as Moores law dictates, technology scaling still continues in recent years. Thus increasing the number of on-chip cores continues to be the facto strategy to scale performance while interconnection networks remain important in multi-core chip systems. In this paper, we present a brand-new network-on-chip (NoC) based on full-mesh architecture - Full-Mesh NoC(FMN) that can provide high connectivity with low-radix routers. We give an example of implementation for a 64-node FMN system in 28 nm process. Results show that this FMN can achieve high frequency of 700 MHz while area requirement of each router is less than 0.035 mm2. At last, we simulate a no-buffered FMN and a buffered FMN under uniform random traffic. Results show that the throughput of the no-buffered FMN can achieve the level of high-radix crossbar. The buffered FMN can achieve 2X throughput compared with the traditional buffered 2D-mesh NoC.

KeywordNetwork On-chip Full-mesh High Connectivity Multi-core
Indexed BySCI
Document Type期刊论文
Corresponding AuthorHongyu,Meng
Affiliation1.Institute of Automation Chinese Academy of Sciences
2.University of Chinese Academy of Sciences
First Author AffilicationInstitute of Automation, Chinese Academy of Sciences
Corresponding Author AffilicationInstitute of Automation, Chinese Academy of Sciences
Recommended Citation
GB/T 7714
Hongyu,Meng,Lei,Yang,Zijun.Liu,et al. A high-throughput network on-chip in full-mesh architecture[J]. IEICE ELEX,2018,15(17):1-12.
APA Hongyu,Meng,Lei,Yang,Zijun.Liu,&Donglin.Wang.(2018).A high-throughput network on-chip in full-mesh architecture.IEICE ELEX,15(17),1-12.
MLA Hongyu,Meng,et al."A high-throughput network on-chip in full-mesh architecture".IEICE ELEX 15.17(2018):1-12.
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