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FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Networks With Efficient DSP and Memory Optimization | |
Li, Jindong1,2; Shen, Guobin2,4; Zhao, Dongcheng2![]() ![]() ![]() | |
发表期刊 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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2023 | |
页码 | 1178 - 1191 |
摘要 | Spiking neural networks (SNNs) have been widely used due to their strong biological interpretability and high-energy efficiency. With the introduction of the backpropagation algorithm and surrogate gradient, the structure of SNNs has become more complex, and the performance gap with artificial neural networks (ANNs) has gradually decreased. However, most SNN hardware implementations for field-programmable gate arrays (FPGAs) cannot meet arithmetic or memory efficiency requirements, which significantly restricts the development of SNNs. They do not delve into the arithmetic operations between the binary spikes and synaptic weights or assume unlimited on-chip RAM resources using overly expensive devices on small tasks. To improve arithmetic efficiency, we analyze the neural dynamics of spiking neurons, generalize the SNN arithmetic operation to the multiplex-accumulate operation, and propose a high-performance implementation of such operation by utilizing the DSP48E2 hard block in Xilinx Ultrascale FPGAs. To improve memory efficiency, we design a memory system to enable efficient synaptic weights and membrane voltage memory access with reasonable on-chip RAM consumption. Combining the above two improvements, we propose an FPGA accelerator that can process spikes generated by the firing neurons on-the-fly (FireFly). FireFly is the first SNN accelerator that incorporates DSP optimization techniques into SNN synaptic operations. FireFly is implemented on several FPGA edge devices with limited resources but still guarantees a peak performance of 5.53 TOP/s at 300 MHz. As a lightweight accelerator, FireFly achieves the highest computational density efficiency compared with existing research using large FPGA devices. |
学科门类 | 工学::控制科学与工程 |
DOI | 10.1109/TVLSI.2023.3279349 |
URL | 查看原文 |
收录类别 | SCI |
七大方向——子方向分类 | 类脑模型与计算 |
国重实验室规划方向分类 | 认知机理与类脑学习 |
是否有论文关联数据集需要存交 | 否 |
引用统计 | |
文献类型 | 期刊论文 |
条目标识符 | http://ir.ia.ac.cn/handle/173211/57243 |
专题 | 脑图谱与类脑智能实验室_类脑认知计算 |
通讯作者 | Zhang, Qian; Zeng, Yi |
作者单位 | 1.School of Artificial Intelligence, University of Chinese Academy of Sciences, Beijing, China 2.Brain-Inspired Cognitive Intelligence Laboratory, Institute of Automation, Chinese Academy of Sciences, Beijing, China 3.Center for Excellence in Brain Science and Intelligence Technology, Chinese Academy of Sciences, Shanghai, China 4.School of Future Technology, University of Chinese Academy of Sciences, Beijing, China |
第一作者单位 | 中国科学院自动化研究所 |
通讯作者单位 | 中国科学院自动化研究所 |
推荐引用方式 GB/T 7714 | Li, Jindong,Shen, Guobin,Zhao, Dongcheng,et al. FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Networks With Efficient DSP and Memory Optimization[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2023:1178 - 1191. |
APA | Li, Jindong,Shen, Guobin,Zhao, Dongcheng,Zhang, Qian,&Zeng, Yi.(2023).FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Networks With Efficient DSP and Memory Optimization.IEEE Transactions on Very Large Scale Integration (VLSI) Systems,1178 - 1191. |
MLA | Li, Jindong,et al."FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Networks With Efficient DSP and Memory Optimization".IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2023):1178 - 1191. |
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TVLSI_FireFly.pdf(5840KB) | 期刊论文 | 作者接受稿 | 开放获取 | CC BY-NC-SA | 浏览 下载 |
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