The demand of program storage space is increasing as the applications become more and more complex. It is usually hard to improve the on-board computer storage capacity due to the high cost and power consumption of the board itself and other relevant systems. The program is compressed to relaxing the problem and then stored in memory, which enhances the logic capacity of the memory and enlarge the memory bandwidth. This thesis introduces a code compression scheme in SOPC design for a processor of on-board computer. Concretely, two strategies of code compression are presented and implemented in FPGA. The main body of our research can be summarized into the following three pieces of work: 1) Research on the storage compression system In this part, the cache design and optimization methods are first discussed by analyzing the hierarchy of storage compression system. The calculation methods of CPU time and the average memory access time are given in this thesis. Then the factors that influence the system performance are analyzed. The methods for evaluating the performances of both CPU and memory access are also assessed. Some new concepts such as distinct code symbols, compressed code symbols and so on have been defined. The code entropy, code joint entropy and condition entropy are proposed. The calculation methods of code message correlation and code source redundancy are introduced. Six mathematical models of the program code symbols are given. They are the domain model, the types of instruction model, performs macro model, code block model, the probability model and hybrid model. Various code compression methods are based on these six models. 2) Research on code compression methods Multi-dictionary based code compression method and the clustered block based code compression method are proposed in this part. According to the frequency disparity of different instructions in the program, the multi-dictionary based code compression method is presented. The method use different dictionaries to encode the instructions. Since the index length of each dictionary is different, the more frequently occurring instructions can be encoded into fewer bits. Theoretical proof and experimental results show that the proposed method is superior to the traditional dictionary compression methods. The compression ratio of MiBench benchmark compiled under the ARM and MIPS instruction sets are between 50%∼52% and 65%∼71% respectively by using multi-dictionary ...
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