浮点 ALU 进行定点与浮点的算术及逻辑运算，是现代数字信号处理器中使用频率最高的运算部件，其运算能力是衡量 DSP 芯片性能的主要指标。浮点 ALU的算法结构以浮点加减算法为基础。成熟的对浮点加减进行优化的算法包括双路径并行，前导 1 预测，并行舍入以及各种快速的定点加法算法。本文对各种优化算法进行了分析比较，针对 DSP 应用的特点做出了改进，并在此基础上采用自顶向下的方法设计了一个用于高性能浮点 DSP 的 ALU（ZKLC ALU）。 传统的双路径并行算法以指数差作为依据将浮点运算划分为两条并行路径执行，去掉了基本算法中关键路径上的一个尾数加法器和一个完整位宽移位器；前导 1 预测算法将前导 1 判断的逻辑提前到与尾数加减并行执行，进一步缩短了关键路径；并行舍入通过复合加法器预先算出所有可能的结果，使舍入步骤简化为选择操作。采用这些优化算法后，将关键路径中的 7 个运算步骤简化为 4个，有效地提高了浮点加减法的运算速度。 由于 DSP 应用中需要大量用到双加减操作，本文提出以加减法作为划分双路径的依据，以在关键路径中增加一个完整位宽移位器为代价，提供了每次操作完成加减运算各一次的能力。设计的 ALU 不支持向±∞舍入，使并行舍入的选择逻辑得到简化，并可舍弃复合加法器前的 n 位半加器，缩短了关键路径。根据复合加法器同时计算 sum 与 sum+1 的特点，采用选择进位的结构来实现，并给出一种选择进位的最优化分组方法。 完成算法设计后，根据 DSP 芯片系统要求 ZKLC ALU 提供的指令功能与外部接口进行电路结构的设计，并使用 VerilogHDL 语言进行 RTL 描述。之后在Cadence Verilog-XL 环境下，用大量测试向量对 ZKLC ALU 进行仿真，并与软件模拟器的运行结果进行比较，验证了 ZKLC ALU 逻辑功能的正确性。最后，使用Synopsys Design Compiler 对设计进行综合，结果显示在 Chartered 1.8V 0.18μmCMOS 工艺下，ZKLC ALU 关键路径的延时约 8.59ns，符合系统设计要求。此外，对不同分组方式下的选择进位复合加法器进行综合的结果也验证了最优化分组方法的正确性。
英文摘要
Floating-point ALU performs arithmetic and logic operations in both fixed-point and floating-point formats. Floating-point ALU is the most important computation unit in modern digital signal processor (DSP) for it is most frequently used. The Architecture of floating-point ALU is based on the algorithms of floating-point arithmetic, such as double datapath, leading-one prediction, parallel rounding and many fast fixed-point adders. This paper analyzed some commonly used optimal algorithms in detail, improved them for DSP application, and then, designed an ALU in high performance floating-point DSP using the Top-Down methodology. Floating-point arithmetic is divided into two parallel parts according to exponent difference in double datapath algorithm, saving a significand adder and a full-length shifter; In leading-one prediction algorithm, the leading-one detection step can be performed in parallel with the significand adder, removing it from the critical path; By selecting the results which are given by the significand compound adder, rounding and addition can be done simultaneously. With these improved algorithms, the number of steps in the critical path is reduced from 7 to 4, hence offering a considerable speed advantage. Because there are so many dual add/subtract operation in DSP application, we proposed a new double datapath algorithm which divided the datapath according to effective addition or subtraction. The new algorithm can operate an addition and a subtraction simultaneously in one cycle only by increasing a full-length shifter in the critical path. ZKLC ALU doesn’t support round to infinity, so the selection of parallel rounding is simplified and the n-bits of half adders can be removed from the critical path. Also, an optimal design of Carry-select compound adder is proposed. We structured the ZKLC ALU according to above algorithms and the system requirements, and described the structure in RTL with VerilogHDL. Then, a simulation in Cadence Verilog-XL was performed to verify the logic function of the ALU. At last, circuit synthesis in Synopsys Design Compiler (Chartered 1.8V 0.18μmCMOS technology) showed a critical path delay of 8.59ns. The result can fulfill the system requirement. Moreover, the optimization of Carry-select compound adder was proved by synthesis results in different stage sizes.
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