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Static timing analysis and its application in IC design
Zhang, Fu-Bin; Ho, Ching-Yen; Peng, Si-Long,
Source PublicationChinese Journal of Electron Devices
2006
Volume29(4)Issue:2006年04期Pages:pp 1329-1333 (EI)
AbstractThis paper addresses static timing analysis and its application in integrate circuits design.Firstly,false paths in static timing analysis and the algorithm to sensitize paths are presented,and then some factors affecting gates and interconnects delay are discussed.Finally,a whole integrate circuits design flow is introduced to emphasize the application of static timing analysis.
KeywordStatic Timing Analysis / sensitize Path / false Path / d-algorithm
Document Type期刊论文
Identifierhttp://ir.ia.ac.cn/handle/173211/12983
Collection智能制造技术与系统研究中心_多维数据分析
Corresponding AuthorZhang, Fu-Bin
Recommended Citation
GB/T 7714
Zhang, Fu-Bin,Ho, Ching-Yen,Peng, Si-Long,. Static timing analysis and its application in IC design[J]. Chinese Journal of Electron Devices,2006,29(4)(2006年04期):pp 1329-1333 (EI).
APA Zhang, Fu-Bin,Ho, Ching-Yen,&Peng, Si-Long,.(2006).Static timing analysis and its application in IC design.Chinese Journal of Electron Devices,29(4)(2006年04期),pp 1329-1333 (EI).
MLA Zhang, Fu-Bin,et al."Static timing analysis and its application in IC design".Chinese Journal of Electron Devices 29(4).2006年04期(2006):pp 1329-1333 (EI).
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