Traffic-Aware and Memory-Aware Task Scheduling on Multi-Core Chips | |
Hongyu,Meng1,2; Yang,Guo1; Zijun.Liu1; Donglin.Wang1 | |
2018-11 | |
会议名称 | 2018 9th IEEE International Conference on Software Engineering and Service Science |
会议日期 | 2018,11.23-25 |
会议地点 | Beijing,China |
摘要 | With the development of semiconductor industry and integrated circuits, the performance of processors has been advanced steadily. More and more devices including cores, memories and peripherals are being integrated in chips to meet the requirements of high performance applications. The rapid increase in chip complexity makes it difficult for these devices to work efficiently. In order to facilitate efficient chips systems, we proposed a task scheduling algorithm for Chip Multi-Processors(CMP) which are called Homogeneous Earliest-Finish-Time(HoEFT) algorithm. We use this algorithm to finish two benchmarks on a chip system consisting of eight Processing Elements(PEs) and a 16MB shared memory. The results show that these PEs can reach reasonable utilization under HoEFT algorithm. |
关键词 | Task Scheduling Multi-core Shared Memory Traffic-aware Memory-aware |
收录类别 | EI |
语种 | 英语 |
文献类型 | 会议论文 |
条目标识符 | http://ir.ia.ac.cn/handle/173211/23628 |
专题 | 国家专用集成电路设计工程技术研究中心 |
通讯作者 | Hongyu,Meng |
作者单位 | 1.Institute of Automation Chinese Academy of Sciences 2.University of Chinese Academy of Sciences |
第一作者单位 | 中国科学院自动化研究所 |
通讯作者单位 | 中国科学院自动化研究所 |
推荐引用方式 GB/T 7714 | Hongyu,Meng,Yang,Guo,Zijun.Liu,et al. Traffic-Aware and Memory-Aware Task Scheduling on Multi-Core Chips[C],2018. |
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文件名称/大小 | 文献类型 | 版本类型 | 开放类型 | 使用许可 | ||
Traffic-Aware and Me(345KB) | 会议论文 | 开放获取 | CC BY-NC-SA | 浏览 下载 |
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