| 英文摘要 | Signal integrity is a major bottleneck in nanometer IC designs. Signal integrity refers to wide varity of problems, which include signal integrity in interconnects and power interity. Signal integrity causes delay or noise at the high-level, but this boils down to resistance, capacitance and inductance（RLC）at circuit level. This thesis researches coupling capacitance crosstalk noise in nanometer IC designs, present static crosstalk noise identification algorithm and dynamic crosstalk noise identification algorithm. Traditional static crosstalk identification methods identify crosstalk targets only using coupling capacitance and noise amplitude information, which lead to the pessimistic results and induce a long time to IC design convergence. In the course of our static crosstalk noise identification, the noise width along with coupling capacitance and noise amplitude are used to identify static crosstalk noise targets, which overcomes the conservative defect of previous methods. In the course of dynamic crosstalk noise identification, hybrid timing analysis is used to provide accurate signal arrival time, which can provide more accurate timing information than static timing analysis. At the same time, a novel test generation is chosen to verify the correlation of signals, so dynamic crosstalk noise can be identified by these accurate timing and logic information. In the course of crosstalk reduction, this paper presents a post-route, crosstalk reduction algorithm by gate and wire sizing. At the same time, it constrains the worst delay of circuit to guarantee circuit performance. This algorithm can minimize total area of circuit subject to worst delay and maximum crosstalk bound, and then it does not lead to timing violation when performing gate and wire sizing. Experimental results demonstrate the effectiveness of the algorithm. What is more, it need not come back to routing phase to reduce crosstalk, so it reduces design iterative number and accelerates the convergence of design. This thesis analyzes power integrity, including static IR drop and dynamic IR drop. What is more, the causes of power noise are discussed and a set of noise reduction methods are presented. Theory analysis and experiment results indicate that the algorithms proposed in this thesis have respective advantages, such as innovation, accuracy, simplicity, applicability, etc. This thesis explores an instructive way to deal with all kinds of signal integrity problems in nanometer IC designs and manufacture. |
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