在深亚微米VLSI设计中，互连性能成为了决定系统性能的关键指标，物理综合工具被用来解决新挑战带来的时序收敛问题。在物理综合过程中，一些关键技术方法被反复使用，其中缓冲优化成为了最为有效的优化互连延时、增强信号完整性、解除耦合效应的技术。与此同时，集成电路的特征尺寸接近曝光系统理论分辨率极限，亚波长光刻的光学临近效应导致晶片上光刻结果相对于原始版图发生畸变现象，业界提出了DFM/DFY设计(Design For Manufacture/ Design For Yield)，其中分辨率增强技术(Resolution Enhancement Technology，RET)能够在一定程度上解决亚波长光刻的失真问题。本文针对上述两个方面的问题开展了如下的研究： 一、随着芯片上缓冲器插入数量的增加，在芯片物理设计互连驱动的布图布局阶段，虽然不需要实际插入缓冲器，但必须考虑互连的缓冲优化才能给出有效的时序分析解。针对这样的情况，本文讨论了闭合解的缓冲器插入算法，给出了改进的统一缓冲优化解，同时针对SOC芯片版图设计要求，提出了非均匀分段和非统一缓冲器插入算法，解决了线网经过大阻挡块时缓冲优化延时的快速计算问题。该算法可以准确的计算长互连线驱动大负载延时，保证设计和时序收敛，并节省布线资源。 二、在后布线阶段的多端线网缓冲优化算法中，本文给出了采用顺序优化流程的考虑版图密度和信号完整性的缓冲插入算法。通过利用考虑延时、摆率和噪声的线网分段最大可行距离计算公式以及考虑版图密度和性能的代价函数，本文给出了缓冲器备选位置快速的标定算法，试验结果表明，算法明显优化了设计密度，提高了缓冲器插入对信号延时、摆率和串扰噪声的修正，节约了缓冲器插入数目和算法运算时间。 三、对版图制造优化的OPC问题进行了研究。提出了基于像素的低复杂度光刻友好掩模设计优化算法，其中包括光刻系统建模、反向光刻问题建模、前向模型近似、光刻友好约束以及ILT迭代优化算法流程。试验结果表明，本文算法给出了低复杂度的光刻友好掩模图形，并且能够对前向OPC给出更多的设计指导原则。
英文摘要
As the process technology advances into the deep sub-micron era, interconnect plays a dominant role in determining circuit performance. Physical synthesis is very effective to keep up with the technology scaling and the timing closure problem. Several key optimization techniques are used throughout the flow, among which, buffer insertion is considered the most effective way for interconnect optimization since it splits high capacitance nets into several small capacitance nets. Buffers can be used not only to improve delay along timing-critical paths, but also to sharpen slew rates and fix capacitance and noise violations. Meanwhile, Deep sub-wavelength imaging is a continuing challenge for the semiconductor industry. Several Resolution Enhancement Techniques (RET) are developed to address the challenge. Among which, Optical and Process Correction (OPC) has attracted a great deal of interest in finding effective method to compensate lithography distortions. This thesis deploys the following research work concerned with the two problems mentioned above: 1, With the increasing number of buffers inserted in the layout, it is necessary to estimate the post-buffering timing results during the floorplan/placement stage to get a more reliable state for the subsequent stage. We discuss the closed form buffer insertion solution which can be applied in the front stage of physical synthesis and give an improved uniform buffering solution. Considering the impact of SOC design, a non-uniform wire segmenting and buffer insertion algorithm is proposed, which can effectively solve the problem of driving wires with heavy load. The algorithm can efficiently solve the large-load-driving problem and save routing resources. 2, We propose a sequential buffer optimization algorithm considering layout density and signal integrity during the post-layout optimization stage. The algorithm includes theoretical results for computing the maximal distance between buffers derived under the timing, noise and slew rate constraints, improved buffer library selection, effective cost function for layout density and k-shortest path buffer candidate location selection algorithm. Experimental results show that the algorithm significantly optimizes the design density and achieve noise reduction and sharp signal slew reconstruction with no impact on total CPU time of buffer insertion. 3, The OPC problem in the VLSI layout manufacturing stage is explored in this thesis. By representing the mas...
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