CASIA OpenIR  > 国家专用集成电路设计工程技术研究中心
MaPU: A Novel Mathematical Computing Architecture
Donglin Wang; Shaolin Xie; Zhiwei Zhang; Xueliang Du; Lei Wang; Zijun Liu; shaolin.xie@ia.ac.cn
2016-03
Conference Namethe 22nd IEEE Symposium on High Performance Computer Architecture
Source Publicationhttp://hpca22.site.ac.upc.edu
Conference DateMarch 12-16 2016
Conference PlaceBarcelona, Spain
PublisherIEEE
Abstract

As the feature size of the semiconductor process is scaling down to 10nm and below, it is possible to assemble systems with high performance processors that can theoretically provide computational power of up to tens of PLOPS. However, the power consumption of these systems is also rocketing up to tens of millions watts, and the actual performance is only around 60% of the theoretical performance. Today, power efficiency and sustained performance have become the main concern of processor designers. Traditional computing architecture such as superscalar and GPGPU are proven to be power inefficient, and there is a big gap between the actual and peak

performance. In this paper, we present the MaPU architecture, a novel architecture which is suitable for data-intensive computing with great power efficiency and sustained computation throughput. To achieve this goal, MaPU attempts to optimize the application from a system perspective, including the hardware, algorithm and corresponding program model. It uses an innovative multi-granularity parallel memory system with intrinsic shuffle ability, cascading pipelines with wide SIMD data paths and a state-machine-based program model. When executing typical signal processing algorithms, a single MaPU core implemented with a 40nm process exhibits a sustained performance of 134 GLOPS while consuming only 2.8 W in power, which increases the actual power efficiency by an order of magnitude comparable with the traditional CPU and GPGPU.

KeywordComputer Architecture Vlsi High Performance Computing
Subject AreaComputer Science
Indexed BySCI
Language英语
Document Type会议论文
Identifierhttp://ir.ia.ac.cn/handle/173211/10916
Collection国家专用集成电路设计工程技术研究中心
Corresponding Authorshaolin.xie@ia.ac.cn
AffiliationInstitute of Automation, Chinese Academy of Sciences
First Author AffilicationInstitute of Automation, Chinese Academy of Sciences
Recommended Citation
GB/T 7714
Donglin Wang,Shaolin Xie,Zhiwei Zhang,et al. MaPU: A Novel Mathematical Computing Architecture[C]:IEEE,2016.
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