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A Fault Masking Dual Module Redundancy Method for FPGA
Zheng, Meisong; Wang, Zilong; Wang, Zilong; Li, Lijian
2016-05
Conference NameCCECE 2016
Source PublicationIEEE Canadian Conferance on Electrical and Computer Engineering
Conference Date2016-5-15
Conference PlaceVancouver, Canada
Abstract ; In order to solve the problem of single-event upset (SEU) in static-random access memory (SRAM) based field-programmable gate arrays (FPGAs), a Fault Masking Dual Module Redundancy (FMDMR) structure is proposed in this paper. The FMDMR method make use of AND/OR logic as dual-module redundancy (DMR) voter. The AND/OR logic are built with unoccupied carry-chains in FPGA; hence no additional hardware overhead are brought about by the insertion of voters. Experiments on MCNC’91 benchmarks show that the FMDMR method can reduce 70% SEU faults on average, with a 2x hardware overhead. It balances between area and reliability, and fits for applications with no rigorous require for reliability. 
KeywordFpga Fault Tolerance Dual Modular Redundancy
Indexed ByEI
Document Type会议论文
Identifierhttp://ir.ia.ac.cn/handle/173211/11747
Collection空天信息研究中心
Corresponding AuthorLi, Lijian
Affiliation中国科学院自动化研究所
Recommended Citation
GB/T 7714
Zheng, Meisong,Wang, Zilong,Wang, Zilong,et al. A Fault Masking Dual Module Redundancy Method for FPGA[C],2016.
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