A Fault Masking Dual Module Redundancy Method for FPGA

CASIA OpenIR > 空天信息研究中心

	A Fault Masking Dual Module Redundancy Method for FPGA
	Zheng, Meisong; Wang, Zilong; Wang, Zilong; Li, Lijian
	2016-05
会议名称	CCECE 2016
会议录名称	IEEE Canadian Conferance on Electrical and Computer Engineering
会议日期	2016-5-15
会议地点	Vancouver, Canada
摘要	; In order to solve the problem of single-event upset (SEU) in static-random access memory (SRAM) based field-programmable gate arrays (FPGAs), a Fault Masking Dual Module Redundancy (FMDMR) structure is proposed in this paper. The FMDMR method make use of AND/OR logic as dual-module redundancy (DMR) voter. The AND/OR logic are built with unoccupied carry-chains in FPGA; hence no additional hardware overhead are brought about by the insertion of voters. Experiments on MCNC’91 benchmarks show that the FMDMR method can reduce 70% SEU faults on average, with a 2x hardware overhead. It balances between area and reliability, and fits for applications with no rigorous require for reliability.
关键词	Fpga Fault Tolerance Dual Modular Redundancy
收录类别	EI
文献类型	会议论文
条目标识符	http://ir.ia.ac.cn/handle/173211/11747
专题	空天信息研究中心
通讯作者	Li, Lijian
作者单位	中国科学院自动化研究所
第一作者单位	中国科学院自动化研究所
推荐引用方式 GB/T 7714	Zheng, Meisong,Wang, Zilong,Wang, Zilong,et al. A Fault Masking Dual Module Redundancy Method for FPGA[C],2016.