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Reliability Oriented Selective Triple Modular Redundancy for SRAM-Based FPGAs
Zheng, Meisong; Wang, Zilong; Tu, Ji; Wang, Junye; Li, Lijian
Source PublicationApplied Mechanics and Materials
2014-11
Issue713-715Pages:1127-1131
AbstractThis paper presents an improved approach to Triple Modular Redundancy (TMR) which concerns don’  t  care  bits  of  LUT  configuration bits and hence classifies the set of LUTs into SEU-sensitive and SEU-insensitive. Unlike the full TMR approach, the improved approach only
triplicates SEU-sensitive LUTs and can greatly reduces the area overhead while maintaining the circuit  reliability.  The  proposed  approach  is  thoroughly  tested  on  the  MCNC’91   benchmarks. Compare with the full TMR method the proposed scheme can reduce the area overhead by 26.6% on average, at the same time the circuit reliability only reduced by 9.1 %. The improved approach can also increase mean time between failures (MTBF) by an average of six times more than the original circuit.   
KeywordFpga Tmr Windowing Seu
Document Type期刊论文
Identifierhttp://ir.ia.ac.cn/handle/173211/11751
Collection空天信息研究中心
Corresponding AuthorLi, Lijian
Affiliation中国科学院自动化研究所
Recommended Citation
GB/T 7714
Zheng, Meisong,Wang, Zilong,Tu, Ji,et al. Reliability Oriented Selective Triple Modular Redundancy for SRAM-Based FPGAs[J]. Applied Mechanics and Materials,2014(713-715):1127-1131.
APA Zheng, Meisong,Wang, Zilong,Tu, Ji,Wang, Junye,&Li, Lijian.(2014).Reliability Oriented Selective Triple Modular Redundancy for SRAM-Based FPGAs.Applied Mechanics and Materials(713-715),1127-1131.
MLA Zheng, Meisong,et al."Reliability Oriented Selective Triple Modular Redundancy for SRAM-Based FPGAs".Applied Mechanics and Materials .713-715(2014):1127-1131.
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