CASIA OpenIR  > 国家专用集成电路设计工程技术研究中心
Path Delay Test generation Toward Activation of worst Case Coupling Effects
minjin, zhang1; Huawei, Li2; Xiaowei,Li2
Source PublicationIEEE Transactions on Very Large Scale Integration (VLSI) Systems
2011-11
Volume19Issue:11Pages:1969-1982
Abstract
; As the feature size scales down, crosstalk noise on
circuit timing becomes increasingly significant. In this paper,
we propose a path delay test generation method toward activation
of worst case crosstalk effects, in order to decrease the test
escape of delay testing. The proposed method performs transition-
map-based timing analysis to identify crosstalk-sensitive
critical paths, followed by a deterministic test generation process.
Using the transition map instead of the timing window to manage
the timing information, the proposed method can identify many
false coupling sites and thus reduce the pessimism in crosstalk-induced
fault collection caused by inaccurate timing analysis. It can
also efficiently calculate the accumulative crosstalk-induced delay,
and find the sub-paths which cause worst case crosstalk effects
during test generation. By converting the timing constraints of
coupling lines into logic constraints, complex timing processing
for crosstalk effect activation is avoided during test generation.
In addition, the tradeoff between accuracy and efficiency can be
explored by varying the size of timescale used in the transition
map.
KeywordCrosstalk-induced Delay Delay Testing Path Delay Fault Signal Integrity Test Generation Timing Analysis
WOS IDWOS:000294869500004
Citation statistics
Cited Times:5[WOS]   [WOS Record]     [Related Records in WOS]
Document Type期刊论文
Identifierhttp://ir.ia.ac.cn/handle/173211/15398
Collection国家专用集成电路设计工程技术研究中心
Affiliation1.Institute of Automation, Chinese Academy of Sciences
2.Institute of Computing Technology, Chinese Academy of Sciences
Recommended Citation
GB/T 7714
minjin, zhang,Huawei, Li,Xiaowei,Li. Path Delay Test generation Toward Activation of worst Case Coupling Effects[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2011,19(11):1969-1982.
APA minjin, zhang,Huawei, Li,&Xiaowei,Li.(2011).Path Delay Test generation Toward Activation of worst Case Coupling Effects.IEEE Transactions on Very Large Scale Integration (VLSI) Systems,19(11),1969-1982.
MLA minjin, zhang,et al."Path Delay Test generation Toward Activation of worst Case Coupling Effects".IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19.11(2011):1969-1982.
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