A novel obstacle-aware multiple fan-out symmetrical clock tree synthesis
Liu, Meng; Zhang, Zhiwei; Sun, Wenqin; Wang, Donglin
2017-10-25
发表期刊IEICE ELECTRONICS EXPRESS
卷号14期号:20
文章类型Article
摘要Clock tree design plays a critical role in improving chip performance and affecting power. In this paper, we propose a novel symmetrical clock tree synthesis algorithm, including tree architecture planning, matching, merging, embedding and buffer insertion. Obstacle-aware placement and routing are also integrated into the algorithm flow. By using NGSPICE simulation for benchmark circuits, our skew results decrease by 17.2% while using less than 24.5% capacitance resource compared with traditional symmetrical clock tree. Further, we also validated the algorithm in ASIC design.
关键词Symmetrical Clock Tree Multiple Fan-out Matching Algorithm Buffer Insertion Obstacle-aware Placement And Routing
WOS标题词Science & Technology ; Technology
DOI10.1587/elex.14.20170935
收录类别SCI
语种英语
项目资助者Chinese Academy of Sciences(XDA-06010402)
WOS研究方向Engineering
WOS类目Engineering, Electrical & Electronic
WOS记录号WOS:000418382100012
引用统计
文献类型期刊论文
条目标识符http://ir.ia.ac.cn/handle/173211/21929
专题国家专用集成电路设计工程技术研究中心
作者单位Univ Chinese Acad Sci, Chinese Acad Sci, Inst Automat, Beijing 100190, Peoples R China
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Liu, Meng,Zhang, Zhiwei,Sun, Wenqin,et al. A novel obstacle-aware multiple fan-out symmetrical clock tree synthesis[J]. IEICE ELECTRONICS EXPRESS,2017,14(20).
APA Liu, Meng,Zhang, Zhiwei,Sun, Wenqin,&Wang, Donglin.(2017).A novel obstacle-aware multiple fan-out symmetrical clock tree synthesis.IEICE ELECTRONICS EXPRESS,14(20).
MLA Liu, Meng,et al."A novel obstacle-aware multiple fan-out symmetrical clock tree synthesis".IEICE ELECTRONICS EXPRESS 14.20(2017).
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