Progress in a novel architecture for high performance processing | |
Zhang, Zhiwei; Liu, Meng; Liu, Zijun; Du, Xueliang; Xie, Shaolin; Ma, Hong; Ding, Guangxin; Ren, Weili; Zhou, Fabiao; Sun, Wenqin; Wang, Huijuan; Wang, Donglin | |
发表期刊 | JAPANESE JOURNAL OF APPLIED PHYSICS |
2018-04-01 | |
卷号 | 57期号:4 |
文章类型 | Article |
摘要 | The high performance processing (HPP) is an innovative architecture which targets on high performance computing with excellent power efficiency and computing performance. It is suitable for data intensive applications like supercomputing, machine learning and wireless communication. An example chip with four application-specific integrated circuit (ASIC) cores which is the first generation of HPP cores has been taped out successfully under Taiwan Semiconductor Manufacturing Company (TSMC) 40 nm low power process. The innovative architecture shows great energy efficiency over the traditional central processing unit (CPU) and general-purpose computing on graphics processing units (GPGPU). Compared with MaPU, HPP has made great improvement in architecture. The chip with 32 HPP cores is being developed under TSMC 16 nm field effect transistor (FFC) technology process and is planed to use commercially. The peak performance of this chip can reach 4.3 teraFLOPS (TFLOPS) and its power efficiency is up to 89.5 gigaFLOPS per watt (GFLOPS/W). (C) 2018 The Japan Society of Applied Physics. |
WOS标题词 | Science & Technology ; Physical Sciences |
DOI | 10.7567/JJAP.57.04FA03 |
收录类别 | SCI ; ISTP |
语种 | 英语 |
项目资助者 | Strategic Pilot Projects of Chinese Academy of Sciences (CAS) |
WOS研究方向 | Physics |
WOS类目 | Physics, Applied |
WOS记录号 | WOS:000430981800004 |
引用统计 | |
文献类型 | 期刊论文 |
条目标识符 | http://ir.ia.ac.cn/handle/173211/22037 |
专题 | 国家专用集成电路设计工程技术研究中心 |
作者单位 | Chinese Acad Sci, Inst Automat, Beijing 100190, Peoples R China |
第一作者单位 | 中国科学院自动化研究所 |
推荐引用方式 GB/T 7714 | Zhang, Zhiwei,Liu, Meng,Liu, Zijun,et al. Progress in a novel architecture for high performance processing[J]. JAPANESE JOURNAL OF APPLIED PHYSICS,2018,57(4). |
APA | Zhang, Zhiwei.,Liu, Meng.,Liu, Zijun.,Du, Xueliang.,Xie, Shaolin.,...&Wang, Donglin.(2018).Progress in a novel architecture for high performance processing.JAPANESE JOURNAL OF APPLIED PHYSICS,57(4). |
MLA | Zhang, Zhiwei,et al."Progress in a novel architecture for high performance processing".JAPANESE JOURNAL OF APPLIED PHYSICS 57.4(2018). |
条目包含的文件 | 条目无相关文件。 |
除非特别说明,本系统中所有内容都受版权保护,并保留所有权利。
修改评论