CASIA OpenIR  > 国家专用集成电路设计工程技术研究中心
Progress in a novel architecture for high performance processing
Zhang, Zhiwei; Liu, Meng; Liu, Zijun; Du, Xueliang; Xie, Shaolin; Ma, Hong; Ding, Guangxin; Ren, Weili; Zhou, Fabiao; Sun, Wenqin; Wang, Huijuan; Wang, Donglin
Source PublicationJAPANESE JOURNAL OF APPLIED PHYSICS
2018-04-01
Volume57Issue:4
SubtypeArticle
AbstractThe high performance processing (HPP) is an innovative architecture which targets on high performance computing with excellent power efficiency and computing performance. It is suitable for data intensive applications like supercomputing, machine learning and wireless communication. An example chip with four application-specific integrated circuit (ASIC) cores which is the first generation of HPP cores has been taped out successfully under Taiwan Semiconductor Manufacturing Company (TSMC) 40 nm low power process. The innovative architecture shows great energy efficiency over the traditional central processing unit (CPU) and general-purpose computing on graphics processing units (GPGPU). Compared with MaPU, HPP has made great improvement in architecture. The chip with 32 HPP cores is being developed under TSMC 16 nm field effect transistor (FFC) technology process and is planed to use commercially. The peak performance of this chip can reach 4.3 teraFLOPS (TFLOPS) and its power efficiency is up to 89.5 gigaFLOPS per watt (GFLOPS/W). (C) 2018 The Japan Society of Applied Physics.
WOS HeadingsScience & Technology ; Physical Sciences
DOI10.7567/JJAP.57.04FA03
Indexed BySCI ; ISTP
Language英语
Funding OrganizationStrategic Pilot Projects of Chinese Academy of Sciences (CAS)
WOS Research AreaPhysics
WOS SubjectPhysics, Applied
WOS IDWOS:000430981800004
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Document Type期刊论文
Identifierhttp://ir.ia.ac.cn/handle/173211/22037
Collection国家专用集成电路设计工程技术研究中心
AffiliationChinese Acad Sci, Inst Automat, Beijing 100190, Peoples R China
Recommended Citation
GB/T 7714
Zhang, Zhiwei,Liu, Meng,Liu, Zijun,et al. Progress in a novel architecture for high performance processing[J]. JAPANESE JOURNAL OF APPLIED PHYSICS,2018,57(4).
APA Zhang, Zhiwei.,Liu, Meng.,Liu, Zijun.,Du, Xueliang.,Xie, Shaolin.,...&Wang, Donglin.(2018).Progress in a novel architecture for high performance processing.JAPANESE JOURNAL OF APPLIED PHYSICS,57(4).
MLA Zhang, Zhiwei,et al."Progress in a novel architecture for high performance processing".JAPANESE JOURNAL OF APPLIED PHYSICS 57.4(2018).
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