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| A reconfigurable computing architecture for 5G communication 期刊论文 Journal of Central South University, 2019, 期号: 0, 页码: 0 作者: GUO Yang; LIU Zi-Jun; YANG Lei; LI Huan; WANG Dong-Lin Adobe PDF(913Kb)  |  收藏  |  浏览/下载:470/142  |  提交时间:2019/07/11 5g Instruction Set Register File Code Compression Throughput Power Consumption. |
| MaPU编程语言及编译器关键技术研究 学位论文 工程硕士, 北京市海淀区中关村东路95号自动化研究所: 中国科学院自动化研究所, 2019 作者: 申俊志 Adobe PDF(4521Kb)  |  收藏  |  浏览/下载:263/1  |  提交时间:2019/06/20 编程语言设计 编译器设计与实现 Vliw 指令调度 |
| A Bypass-Based Low Latency Network-on-Chip Router 期刊论文 IEICE Electronics Express, 2019, 卷号: 16, 期号: 4, 页码: 1 作者: Guo Peng; Qingbin Liu; Ruizhi Chen; Lei Yang; Donglin Wang Adobe PDF(1881Kb)  |  收藏  |  浏览/下载:307/99  |  提交时间:2019/06/17 Network-on-chip Router Bypass Low Latency |
| A Distributed Register File Architecture Based on Dynamic Scheduling for VLIW Machine 会议论文 , 北京, 2018-6 作者: Yang Guo; Donglin Wang; Zijun Liu; Hongyu Meng 浏览  |  Adobe PDF(203Kb)  |  收藏  |  浏览/下载:331/131  |  提交时间:2019/05/10 |
| A high-throughput network on-chip in full-mesh architecture 期刊论文 IEICE ELEX, 2018, 卷号: 15, 期号: 17, 页码: 1-12 作者: Hongyu,Meng; Lei,Yang; Zijun.Liu; Donglin.Wang 浏览  |  Adobe PDF(2525Kb)  |  收藏  |  浏览/下载:311/109  |  提交时间:2019/05/06 Network On-chip Full-mesh High Connectivity Multi-core |
| Advanced Extensible Crossbar Protocol for Connecting Multi-Cores and Shared-Memory on Chip 会议论文 , Beijing,China, 2018,6.15-17 作者: Hongyu,Meng; Donglin,Wang; Zijun,Liu; Yang,Guo 浏览  |  Adobe PDF(318Kb)  |  收藏  |  浏览/下载:336/115  |  提交时间:2019/05/06 Interconnect Crossbar Multi-cores Shared-memory |
| 无权访问的条目 会议论文 作者: Meng Liu; Zhiwei Zhang; Wenqin Sun; Donglin Wang Adobe PDF(157Kb)  |  收藏  |  浏览/下载:37/1  |  提交时间:2019/01/15 |
| 微处理器时钟网络设计的关键技术研究 学位论文 , 北京: 中国科学院大学, 2018 作者: 刘檬 Adobe PDF(20426Kb)  |  收藏  |  浏览/下载:163/13  |  提交时间:2019/01/08 计算机体系结构 集成电路设计 时钟网络 |
| Inductorless SiGe BiCMOS optical receiver frond end for 25 Gb/s optical links 会议论文 , 成都, October 21-22, 2016 作者: Jingqiu Wang; Fujiang Lin; Liang Chen; Qiwei Song 浏览  |  Adobe PDF(589Kb)  |  收藏  |  浏览/下载:446/214  |  提交时间:2017/09/30 Sige Bicmos Optical Receiver Inductorless Zero-pole Canceling Negative Miller Capacitance |
| Path Delay Test generation Toward Activation of worst Case Coupling Effects 期刊论文 IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011, 卷号: 19, 期号: 11, 页码: 1969-1982 作者: minjin, zhang; Huawei, Li; Xiaowei,Li 浏览  |  Adobe PDF(345Kb)  |  收藏  |  浏览/下载:255/113  |  提交时间:2017/09/19 Crosstalk-induced Delay Delay Testing Path Delay Fault Signal Integrity Test Generation Timing Analysis |