CASIA OpenIR
(本次检索基于用户作品认领结果)

浏览/检索结果: 共14条,第1-10条 帮助

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A reconfigurable computing architecture for 5G communication 期刊论文
Journal of Central South University, 2019, 期号: 0, 页码: 0
作者:  GUO Yang;  LIU Zi-Jun;  YANG Lei;  LI Huan;  WANG Dong-Lin
浏览  |  Adobe PDF(913Kb)  |  收藏  |  浏览/下载:479/144  |  提交时间:2019/07/11
5g  Instruction Set  Register File  Code Compression  Throughput  Power Consumption.  
Accelerate Convolutional Neural Network with a customized VLIW DSP 会议论文
, 北京, 2018-10
作者:  Guo Peng;  Ma Hong;  Guo Ruoshan;  Liu Zhuang;  Li Pin;  Wang Donglin
浏览  |  Adobe PDF(1173Kb)  |  收藏  |  浏览/下载:364/135  |  提交时间:2019/06/17
A Bypass-Based Low Latency Network-on-Chip Router 期刊论文
IEICE Electronics Express, 2019, 卷号: 16, 期号: 4, 页码: 1
作者:  Guo Peng;  Qingbin Liu;  Ruizhi Chen;  Lei Yang;  Donglin Wang
浏览  |  Adobe PDF(1881Kb)  |  收藏  |  浏览/下载:319/102  |  提交时间:2019/06/17
Network-on-chip  Router  Bypass  Low Latency  
Parallel Polar Encoding in 5G Communication 会议论文
, 巴西纳塔尔, 2018-6
作者:  Yang Guo;  Shaolin Xie;  Zijun Liu;  Lei Yang;  Donglin Wang
浏览  |  Adobe PDF(377Kb)  |  收藏  |  浏览/下载:367/123  |  提交时间:2019/05/10
A Design Space Exploration Method for on-Chip Memory System Based on Task Scheduling 会议论文
, Beijing,China, 2018,11.23-25
作者:  Hongyu,Meng;  Pengfei.Ding;  Mingxuan.Wang;  Donglin.Wang
浏览  |  Adobe PDF(288Kb)  |  收藏  |  浏览/下载:311/109  |  提交时间:2019/05/06
Design Space Exploration  Multi-core Architecture  Memory System  Task Scheduling  
Advanced Extensible Crossbar Protocol for Connecting Multi-Cores and Shared-Memory on Chip 会议论文
, Beijing,China, 2018,6.15-17
作者:  Hongyu,Meng;  Donglin,Wang;  Zijun,Liu;  Yang,Guo
浏览  |  Adobe PDF(318Kb)  |  收藏  |  浏览/下载:344/118  |  提交时间:2019/05/06
Interconnect  Crossbar  Multi-cores  Shared-memory  
无权访问的条目 会议论文
作者:  Meng Liu;  Zhiwei Zhang;  Wenqin Sun;  Donglin Wang
Adobe PDF(246Kb)  |  收藏  |  浏览/下载:27/2  |  提交时间:2019/01/15
Progress in a novel architecture for high performance processing 期刊论文
JAPANESE JOURNAL OF APPLIED PHYSICS, 2018, 卷号: 57, 期号: 4
作者:  Zhang, Zhiwei;  Liu, Meng;  Liu, Zijun;  Du, Xueliang;  Xie, Shaolin;  Ma, Hong;  Ding, Guangxin;  Ren, Weili;  Zhou, Fabiao;  Sun, Wenqin;  Wang, Huijuan;  Wang, Donglin
收藏  |  浏览/下载:324/0  |  提交时间:2018/10/10
A reconfigurable ASIC-like image polyphase interpolation implementation method 会议论文
, ShenZhen, 2017-7
作者:  Lei Yang;  Ruoshan Guo;  Shaolin Xie;  Donglin Wang
Adobe PDF(210Kb)  |  收藏  |  浏览/下载:368/124  |  提交时间:2018/05/07
Image Interpolation  Acceleration  Reconfigurable Implementation  
An automatic and practical flow for clock tree construction in physical design 会议论文
, Beijing, 26-28 Aug. 2016
作者:  Meng Liu;  Wenqin Sun;  Wuqi Wang;  Zhiwei Zhang;  Donglin Wang
Adobe PDF(825Kb)  |  收藏  |  浏览/下载:509/216  |  提交时间:2017/10/09