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| Parallel LDPC Decoder Based on Low-Complexity Corrected Min Sum Algorithm 会议论文 , Suzhou, China, 2022-4-23 作者: Sun, Yisong; Li, Huan; Zhang, Xinyu; Guo, Chen; Liu, Zijun; Wang, Donglin Adobe PDF(370Kb)  |  收藏  |  浏览/下载:270/71  |  提交时间:2022/06/14 5G LDPC decoder LCC-MS UCP |
| A reconfigurable computing architecture for 5G communication 期刊论文 Journal of Central South University, 2019, 期号: 0, 页码: 0 作者: GUO Yang; LIU Zi-Jun; YANG Lei; LI Huan; WANG Dong-Lin 浏览  |  Adobe PDF(913Kb)  |  收藏  |  浏览/下载:452/137  |  提交时间:2019/07/11 5g Instruction Set Register File Code Compression Throughput Power Consumption. |
| A Distributed Register File Architecture Based on Dynamic Scheduling for VLIW Machine 会议论文 , 北京, 2018-6 作者: Yang Guo; Donglin Wang; Zijun Liu; Hongyu Meng 浏览  |  Adobe PDF(203Kb)  |  收藏  |  浏览/下载:308/123  |  提交时间:2019/05/10 |
| Parallel Polar Encoding in 5G Communication 会议论文 , 巴西纳塔尔, 2018-6 作者: Yang Guo; Shaolin Xie; Zijun Liu; Lei Yang; Donglin Wang 浏览  |  Adobe PDF(377Kb)  |  收藏  |  浏览/下载:337/115  |  提交时间:2019/05/10 |
| A reconfigurable high-performance multiplier based on multi-granularity design and parallel acceleration 会议论文 , 中国科技会堂, 2017-11 作者: Feng Jing; Zijun Liu; Xiaojun Ma; Guo Yang; Guo Peng; Donglin Wang 浏览  |  Adobe PDF(576Kb)  |  收藏  |  浏览/下载:512/202  |  提交时间:2018/05/31 Compression High Speed Multi-granularity Parallel Power Efficient Reuse Reconfigurable |
| MaPU: A Novel Mathematical Computing Architecture 会议论文 http://hpca22.site.ac.upc.edu, Barcelona, Spain, March 12-16 2016 作者: Donglin Wang; Shaolin Xie; Zhiwei Zhang; Xueliang Du; Lei Wang; Zijun Liu; shaolin.xie@ia.ac.cn 浏览  |  Adobe PDF(2051Kb)  |  收藏  |  浏览/下载:745/189  |  提交时间:2016/04/07 Computer Architecture Vlsi High Performance Computing |
| 多维DMA传输装置与方法 专利 专利类型: 发明, 专利号: CN201110449966.X, 申请日期: 2011-12-29, 公开日期: 2012-07-11 发明人: 王东琳; 刘子君; 张星; 谢少林 Adobe PDF(586Kb)  |  收藏  |  浏览/下载:199/22  |  提交时间:2015/09/22 |