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A High-Efficiency FPGA-Based Accelerator for Binarized Neural Network 期刊论文
Journal of Circuits, Systems, and Computers, 2019, 卷号: 28, 期号: 1, 页码: 1
作者:  Guo Peng;  Ma Hong;  Ruizhi Chen;  Donglin Wang
浏览  |  Adobe PDF(1487Kb)  |  收藏  |  浏览/下载：306/135  |  提交时间：2019/06/17
Cnn  Bnn  Fpga  Accelerator  
Traffic-Aware and Memory-Aware Task Scheduling on Multi-Core Chips 会议论文
, Beijing,China, 2018,11.23-25
作者:  Hongyu,Meng;  Yang,Guo;  Zijun.Liu;  Donglin.Wang
浏览  |  Adobe PDF(345Kb)  |  收藏  |  浏览/下载：291/96  |  提交时间：2019/05/06
Task Scheduling  Multi-core  Shared Memory  Traffic-aware  Memory-aware  
A Design Space Exploration Method for on-Chip Memory System Based on Task Scheduling 会议论文
, Beijing,China, 2018,11.23-25
作者:  Hongyu,Meng;  Pengfei.Ding;  Mingxuan.Wang;  Donglin.Wang
浏览  |  Adobe PDF(288Kb)  |  收藏  |  浏览/下载：281/100  |  提交时间：2019/05/06
Design Space Exploration  Multi-core Architecture  Memory System  Task Scheduling  
Accelerate Convolutional Neural Network with a customized VLIW DSP 会议论文
, 北京, 2018-10
作者:  Guo Peng;  Ma Hong;  Guo Ruoshan;  Liu Zhuang;  Li Pin;  Wang Donglin
浏览  |  Adobe PDF(1173Kb)  |  收藏  |  浏览/下载：320/122  |  提交时间：2019/06/17
Optimal Many-to-Many Personalized Concurrent Communication in RapidIO-based Fat-trees 会议论文
17th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing (SNPD 2016), Shanghai,China, 2016.05.30-2016.06.01
作者:  Shu Lin;  Hao,Jie;  Song,Yafang;  Li,Chengcheng;  Wang,Donglin;  Shu,Lin
浏览  |  Adobe PDF(775Kb)  |  收藏  |  浏览/下载：352/59  |  提交时间：2016/06/27
Many-to-many  Personalized  Rapidio  Fat-tree  Node-level  Congestion-avoidance  
MaPU: A Novel Mathematical Computing Architecture 会议论文
http://hpca22.site.ac.upc.edu, Barcelona, Spain, March 12-16 2016
作者:  Donglin Wang;  Shaolin Xie;  Zhiwei Zhang;  Xueliang Du;  Lei Wang;  Zijun Liu;  shaolin.xie@ia.ac.cn
浏览  |  Adobe PDF(2051Kb)  |  收藏  |  浏览/下载：726/184  |  提交时间：2016/04/07
Computer Architecture  Vlsi  High Performance Computing